Author Topic: Switch macro timings  (Read 1725 times)

hutch--

  • Administrator
  • Member
  • ******
  • Posts: 4561
  • Mnemonic Driven API Grinder
    • The MASM32 SDK
Re: Switch macro timings
« Reply #15 on: April 29, 2016, 09:46:32 PM »
Each has its advantage, try a table based sequence of 10 1000 1000000 100000000 and you will see why a normal sequential comparison switch is more general purpose. Table based switch statements must work on stored addresses and with wide disparity of value that tables become massive.
hutch at movsd dot com
http://www.masm32.com    :biggrin:  :biggrin:

TWell

  • Member
  • ****
  • Posts: 735
Re: Switch macro timings
« Reply #16 on: April 29, 2016, 11:38:34 PM »
Code: [Select]
AMD Athlon(tm) II X2 220 Processor 2.8 Ghz
Assembled with AsmC
Result MB:      0, 25 ms
Result Masm32:  0, 2708 ms
Result AsmC:    0, 18 ms

14084   bytes for swMB
27540   bytes for swMasm32
22111   bytes for swAsmC
-- Tim, not a assembler programmer

jj2007

  • Member
  • *****
  • Posts: 7206
  • Assembler is fun ;-)
    • MasmBasic
Re: Switch macro timings
« Reply #17 on: June 16, 2017, 09:38:44 PM »
Nice "deep" article on switch: From Switch Statement Down to Machine Code by Vlad Lazarenko (credits to Frankie at Pelles C).

hutch--

  • Administrator
  • Member
  • ******
  • Posts: 4561
  • Mnemonic Driven API Grinder
    • The MASM32 SDK
Re: Switch macro timings
« Reply #18 on: June 27, 2017, 07:08:06 PM »
 :biggrin:

Try a "switch" statement with a number range like "0, 2gig, 4gig" and see which algo is faster.  :P
hutch at movsd dot com
http://www.masm32.com    :biggrin:  :biggrin: