64 bit assembler > 64 Bit Assembler

unknown argument type -> xmm0

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markallyn:
Hello everyone,

Ah yes, still the steep learning curve is still steep.

I have no idea why ML64 is claiming that the XMM0 register is an "unknown argument type" when it hits the following couple of lines:

--- Quote ---{prolog}

sub rsp, 30h
movsd  xmm0, pie ;pie is declared a real8 in 3.14159 in data segment
invoke printf, ADDR format, xmm0

...
{epilog}


--- End quote ---

I must be doing something stupid because using CPUID it is clear that the SSE technology is there on the board.

Regards,
Mark Allyn

jj2007:
Mark,
The problem is probably the CRT. This code works just fine:
--- Code: ---include \Masm32\MasmBasic\Res\JBasic.inc
.code
pie REAL8 3.141592653589793238
Init
  movsd  xmm0, pie ;pie is declared a real8 in 3.14159 in data segment
  usedeb=1
  deb 4, "PI in xmm0", f:xmm0
  Inkey Chr$("This code was assembled with ", @AsmUsed$(1), " in ", jbit$, "-bit format")
EndOfCode
--- End code ---

Output:
--- Code: ---PI in xmm0      f:xmm0  3.141592654
This code was assembled with ml64 in 64-bit format
--- End code ---

markallyn:
Hi JJ,

Thanks for responding.  I do appreciate it!  After considerable messing around it turned out that the problem was coming from the invoke macro.  Invoke doesn't appear to "know" the sse registers.  If I use a call printf instruction, then printf  "sort of" works. I use the qualifier "sort of" because the xmm0 register must first be placed in a gp register--in this case rdx (rcx contains the format).  In other words, printf doesn't seem to know the sse registers for floats.  don't understand why this is going on.  If you can enlighten me on this point it would be very informative for me.

The other puzzling feature of this concerns the rax register.  In linux systems rax contains the number of sse registers in a variadic function.   Apparently, this isn't the case with masm 64.  Am I wrong?

Regards,
Mark

hutch--:
The "invoke" macro is written in accordance with the Microsoft ABI which directly handles from BYTE to QWORD as register/stack arguments. When you use SSE or AVX registers you load the directly and use the CALL mnemonic.

aw27:

--- Quote ---I must be doing something stupid because using CPUID it is clear that the SSE technology is there on the board.

--- End quote ---
All x64 CPUs support at least SSE2.

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