The archive cpu.zip contains 3 files:
cpu.asm (assembly language source), cpu.exe (the running 64 bit console application) and build_cpu.bat (builds the application).
The output of the program depends on the machine it is running on. It outputs a few information about the processor. This is the result on my Windows 10 computer:
CPU strings:
------------
Processor Vendor String: GenuineIntel
Processor Brand String: Intel(R)Core(TM)i7-7820XCPU@3.60GHz
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX AVX2 AVX-512 F
It's safe to use the following AVX-512 extensions with this machine:
--------------------------------------------------------------------
AVX-512 DQ : Vector Double Word and Quad Word
AVX-512 CD : Efficient conflict detection to allow more loops to be vectorized.
AVX-512 BW : Extends AVX-512 to cover 8-bit and 16-bit integer operations.
AVX-512 VL : Extends most AVX-512 operations to also operate on XMM and YMM registers.
Any processor that implements any portion of the AVX-512 extensions MUST implement AVX-512 F.
Not every architecture has all the instruction sets built in. We've for example:
Knights Landing : CD ER PF
Knights Mill : CD ER PF 4FMAPS 4VNNIW VPOPCNTDQ
Skylake : CD VL DQ BW
Cannon Lake : CD VL DQ BW IFMA VBMI
Cascade Lake : CD VL DQ BW VNNI
Ice Lake : CD VL DQ BW IFMA VBMI VBMI2 VPOPCNTDQ BITALG VNNI VPCLMULQDQ GFNI VAES
Tiger Lake : CD VL DQ BW IFMA VBMI VBMI2 VPOPCNTDQ BITALG VNNI VPCLMULQDQ GFNI VAES VP2INTERSECT
Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------
RDRAND : Returning random numbers from an on-chip hardware random number generator.
AESNI : Advanced Encryption Standard Instruction Set
VMX : Virtual Machine Extensions
FPU : Floating Point Unit on chip
VME : Virtual 8086 Mode Enhancements
DE : Debugging Extensions. Support for I/O breakpoints.
PSE : Page Size Extension
TSC : Time Stamp Counter. The RDTSC instruction is supported.
MSR : Model Specific Registers RDMSR and WRMSR Instructions.
PAE : Physical Address Extension
CX8 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is supported.
APIC : The processor contains an Advanced Programmable Interrupt Controller (APIC) on board.
The program is started normally with cpu or cpu.exe from the command line. Since quite a lot may be displayed, you have to scroll a bit to be able to read everything. Alternatively, you can launch the application in full-screen mode.
The third variant is to use a pipe, something like this:
cpu.exe>cpu.txt
With other processors, a different output will naturally result. I don't want to be nosy, but results from other forum members would be helpful. Thanks in advance.
Gunther
This is my result. The only difference from the result is that I have the 5820k clocked at 4 gig.
CPU strings:
------------
Processor Vendor String: GenuineIntel
Processor Brand String: Intel(R)Core(TM)i7-5820KCPU@3.30GHz
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX AVX2
Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------
RDRAND : Returning random numbers from an on-chip hardware random number generator.
AESNI : Advanced Encryption Standard Instruction Set
VMX : Virtual Machine Extensions
FPU : Floating Point Unit on chip
VME : Virtual 8086 Mode Enhancements
DE : Debugging Extensions. Support for I/O breakpoints.
PSE : Page Size Extension
TSC : Time Stamp Counter. The RDTSC instruction is supported.
MSR : Model Specific Registers RDMSR and WRMSR Instructions.
PAE : Physical Address Extension
CX8 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is supported.
APIC : The processor contains an Advanced Programmable Interrupt Controller (APIC) on board.
Hi,
Two laptops.
CPU strings:
------------
Processor Vendor String: GenuineIntel
Processor Brand String: Intel(R)Core(TM)i3-4005UCPU@1.70GHz
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX AVX2
Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------
RDRAND : Returning random numbers from an on-chip hardware random number generator.
AESNI : Advanced Encryption Standard Instruction Set
VMX : Virtual Machine Extensions
FPU : Floating Point Unit on chip
VME : Virtual 8086 Mode Enhancements
DE : Debugging Extensions. Support for I/O breakpoints.
PSE : Page Size Extension
TSC : Time Stamp Counter. The RDTSC instruction is supported.
MSR : Model Specific Registers RDMSR and WRMSR Instructions.
PAE : Physical Address Extension
CX8 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is supported.
APIC : The processor contains an Advanced Programmable Interrupt Controller (APIC) on board.
CPU strings:
------------
Processor Vendor String: GenuineIntel
Processor Brand String: Intel(R)Core(TM)i3-10110UCPU@2.10GHz
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX AVX2
Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------
RDRAND : Returning random numbers from an on-chip hardware random number generator.
AESNI : Advanced Encryption Standard Instruction Set
VMX : Virtual Machine Extensions
FPU : Floating Point Unit on chip
VME : Virtual 8086 Mode Enhancements
DE : Debugging Extensions. Support for I/O breakpoints.
PSE : Page Size Extension
TSC : Time Stamp Counter. The RDTSC instruction is supported.
MSR : Model Specific Registers RDMSR and WRMSR Instructions.
PAE : Physical Address Extension
CX8 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is supported.
APIC : The processor contains an Advanced Programmable Interrupt Controller (APIC) on board.
Regards,
Steve N.
wine cpu.exe
CPU strings:
------------
Processor Vendor String: GenuineIntel
Processor Brand String: Intel(R)Core(TM)i7-6700CPU@3.40GHz
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX AVX2
Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------
RDRAND : Returning random numbers from an on-chip hardware random number generator.
AESNI : Advanced Encryption Standard Instruction Set
VMX : Virtual Machine Extensions
SMX : Safer Mode Extensions
FPU : Floating Point Unit on chip
VME : Virtual 8086 Mode Enhancements
DE : Debugging Extensions. Support for I/O breakpoints.
PSE : Page Size Extension
TSC : Time Stamp Counter. The RDTSC instruction is supported.
MSR : Model Specific Registers RDMSR and WRMSR Instructions.
PAE : Physical Address Extension
CX8 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is supported.
APIC : The processor contains an Advanced Programmable Interrupt Controller (APIC) on board.
QuoteCPU strings:
------------
Processor Vendor String: GenuineIntel
Processor Brand String: Intel(R)Core(TM)i5-9400HCPU@2.50GHz
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX AVX2
Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------
RDRAND : Returning random numbers from an on-chip hardware random number generator.
AESNI : Advanced Encryption Standard Instruction Set
VMX : Virtual Machine Extensions
SMX : Safer Mode Extensions
FPU : Floating Point Unit on chip
VME : Virtual 8086 Mode Enhancements
DE : Debugging Extensions. Support for I/O breakpoints.
PSE : Page Size Extension
TSC : Time Stamp Counter. The RDTSC instruction is supported.
MSR : Model Specific Registers RDMSR and WRMSR Instructions.
PAE : Physical Address Extension
CX8 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is supported.
APIC : The processor contains an Advanced Programmable Interrupt Controller (APIC) on board.
Thanks for using this small application going to: Steve (aka Hutch), Steve N. (aka FORTRANS), mineiro, six_L. :thumbsup:
The program will hopefully be helpful for some other programmers. I am now working on structuring it better, testing the rest and also recognizing the new instructions announced by Intel.
I mean in particular AMX (Advanced Matrix Extensions (https://fuse.wikichip.org/news/3600/the-x86-advanced-matrix-extension-amx-brings-matrix-operations-to-debut-with-sapphire-rapids/)).
Gunther
CPU strings:
------------
Processor Vendor String: GenuineIntel
Processor Brand String: Intel(R)Core(TM)i5CPU650@3.20GHz
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2
Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------
AESNI : Advanced Encryption Standard Instruction Set
VMX : Virtual Machine Extensions
SMX : Safer Mode Extensions
FPU : Floating Point Unit on chip
VME : Virtual 8086 Mode Enhancements
DE : Debugging Extensions. Support for I/O breakpoints.
PSE : Page Size Extension
TSC : Time Stamp Counter. The RDTSC instruction is supported.
MSR : Model Specific Registers RDMSR and WRMSR Instructions.
PAE : Physical Address Extension
CX8 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is sup
ported.
APIC : The processor contains an Advanced Programmable Interrupt Controller (APIC) on board.
Nice program, thanks Gunther for sharing it :thup:. It's nice to have you back. :mrgreen:
CPU strings:
------------
Processor Vendor String: GenuineIntel
Processor Brand String: Intel(R)Core(TM)i5-2450MCPU@2.50GHz
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX
Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------
AESNI : Advanced Encryption Standard Instruction Set
VMX : Virtual Machine Extensions
FPU : Floating Point Unit on chip
VME : Virtual 8086 Mode Enhancements
DE : Debugging Extensions. Support for I/O breakpoints.
PSE : Page Size Extension
TSC : Time Stamp Counter. The RDTSC instruction is supported.
MSR : Model Specific Registers RDMSR and WRMSR Instructions.
PAE : Physical Address Extension
CX8 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is supported.
APIC : The processor contains an Advanced Programmable Interrupt Controller (APIC) on board.
Very nice, Gunther :thumbsup:
For comparison, PrintCpu (https://www.jj2007.eu/MasmBasicQuickReference.htm#Mb1401) yields a simpler
Intel(R) Core(TM) i5-2450M CPU @ 2.50GHz (MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX)
Thanks to Felipe and Jochen. :thumbsup:
Quote from: felipe on February 03, 2021, 09:47:07 AM
Nice program, thanks Gunther for sharing it :thup:. It's nice to have you back. :mrgreen:
I think it could be better. Especially the procedure Iset is too overloaded. I have already fixed this in the new version. In addition, not all AVX-512 extensions are currently queried properly. I'm in the process of fixing that right now.
We need this routine for the fractal compression at CERN. At the moment, it still runs with FPU code. But we have now set up different code paths in the new version. So I have now written everything to be callable from C or C++.
This should always be kept in mind when judging the source. As a pure assembly language application, I would solve some things differently. Of course, all these variables and flags are only needed at runtime to select the
correct code path. I only do the output for the version here in the forum. Maybe this helps the one or the other programmer?
It's pretty intricate. The PC farm at CERN, with over 20 000 computers and more than 30 000 cores, is very heterogeneous. There are historical reasons for this, which I will not go into here.
Quote from: jj2007 on February 03, 2021, 12:21:27 PM
Very nice, Gunther :thumbsup:
For comparison, PrintCpu (https://www.jj2007.eu/MasmBasicQuickReference.htm#Mb1401) yields a simpler
Intel(R) Core(TM) i5-2450M CPU @ 2.50GHz (MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX)
As already said above: It still has weaknesses and could be better.
Please wait for the next version.
Gunther
Hi Gunther,
my results :thumbsup:
CPU strings:
------------
Processor Vendor String: GenuineIntel
Processor Brand String: Intel(R)Core(TM)i7-4810MQCPU@2.80GHz
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX AVX2
Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------
RDRAND : Returning random numbers from an on-chip hardware random number generator.
AESNI : Advanced Encryption Standard Instruction Set
VMX : Virtual Machine Extensions
SMX : Safer Mode Extensions
FPU : Floating Point Unit on chip
VME : Virtual 8086 Mode Enhancements
DE : Debugging Extensions. Support for I/O breakpoints.
PSE : Page Size Extension
TSC : Time Stamp Counter. The RDTSC instruction is supported.
MSR : Model Specific Registers RDMSR and WRMSR Instructions.
PAE : Physical Address Extension
CX8 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is supported.
APIC : The processor contains an Advanced Programmable Interrupt Controller (APIC) on board.
CPU strings:
------------
Processor Vendor String: AuthenticAMD
Processor Brand String: AMDRyzen53400GwithRadeonVegaGraphics
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX AVX2
Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------
RDRAND : Returning random numbers from an on-chip hardware random number generator.
AESNI : Advanced Encryption Standard Instruction Set
FPU : Floating Point Unit on chip
VME : Virtual 8086 Mode Enhancements
DE : Debugging Extensions. Support for I/O breakpoints.
PSE : Page Size Extension
TSC : Time Stamp Counter. The RDTSC instruction is supported.
MSR : Model Specific Registers RDMSR and WRMSR Instructions.
PAE : Physical Address Extension
CX8 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is supported.
APIC : The processor contains an Advanced Programmable Interrupt Controller (APIC) on board.
Thanks to LiaoMi and TimoVJL for testing. :thumbsup: It seems to work with AMD processors, too. That's good news.
Gunther
Quote from: Gunther on February 03, 2021, 02:13:03 PMThe PC farm at CERN, with over 20 000 computers and more than 30 000 cores, is very heterogeneous. There are historical reasons for this, which I will not go into here.
Quote from: jj2007 on February 03, 2021, 12:21:27 PM
Very nice, Gunther :thumbsup:
For comparison, PrintCpu (https://www.jj2007.eu/MasmBasicQuickReference.htm#Mb1401) yields a simpler
Intel(R) Core(TM) i5-2450M CPU @ 2.50GHz (MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX)
As already said above: It still has weaknesses and could be better.
It's working fine :thumbsup:
For testing if an application can run on one of your 20,000 machines, you could write a macro (or a proc for C) like
WillRunFine(bitmask) that returns true or false.
Jochen,
Quote from: jj2007 on February 03, 2021, 08:56:16 PM
It's working fine :thumbsup:
For testing if an application can run on one of your 20,000 machines, you could write a macro (or a proc for C) like WillRunFine(bitmask) that returns true or false.
probably a function, which can check the needed variables to select the corresponding code path. Another possibility would be Intel's CPU dispatch (https://software.intel.com/content/www/us/en/develop/articles/understanding-cpu-optimized-code-used-in-intel-ipp.html). But one would need the Intel compiler and the question is: What will the Intel compiler do on an AMD processor?
Gunther
bit late ...but
CPU strings:
------------
Processor Vendor String: GenuineIntel
Processor Brand String: Intel(R)Xeon(R)CPUX5670@2.93GHz
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2
Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------
AESNI : Advanced Encryption Standard Instruction Set
VMX : Virtual Machine Extensions
SMX : Safer Mode Extensions
FPU : Floating Point Unit on chip
VME : Virtual 8086 Mode Enhancements
DE : Debugging Extensions. Support for I/O breakpoints.
PSE : Page Size Extension
TSC : Time Stamp Counter. The RDTSC instruction is supported.
MSR : Model Specific Registers RDMSR and WRMSR Instructions.
PAE : Physical Address Extension
CX8 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is supported.
APIC : The processor contains an Advanced Programmable Interrupt Controller (APIC) on board.
regards mike
Another AMD ...
CPU strings:
------------
Processor Vendor String: AuthenticAMD
Processor Brand String: AMDRyzen73700X8-CoreProcessor
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX AVX2
Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------
RDRAND : Returning random numbers from an on-chip hardware random number generator.
AESNI : Advanced Encryption Standard Instruction Set
FPU : Floating Point Unit on chip
VME : Virtual 8086 Mode Enhancements
DE : Debugging Extensions. Support for I/O breakpoints.
PSE : Page Size Extension
TSC : Time Stamp Counter. The RDTSC instruction is supported.
MSR : Model Specific Registers RDMSR and WRMSR Instructions.
PAE : Physical Address Extension
CX8 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is supported.
APIC : The processor contains an Advanced Programmable Interrupt Controller (APIC) on board.
Kind regards
Greenhorn
My thanks to mikeburr and Greenhorn for the test results.
Quote from: Greenhorn on February 05, 2021, 09:47:57 AM
Another AMD ...
Why not? It is supposed to be quite a decent processor.
Quote from: mikeburr on February 05, 2021, 08:55:28 AM
bit late ...but
It's never too late.
Later today I'll finish the revised version of the program. There are some small bugs fixed, the number of procedure calls is reduced and more features and instruction sets are checked.
Gunther
As promised, here is the revised version of CPU. The new archive is called cpuNew1.zip and is under the first post of this thread.
I fixed some small bugs, reduced the number of procedure calls, and the application tests for more instructions and features. Here is the output on my large machine.
Quote
CPU strings:
------------
Processor Vendor String: GenuineIntel
Processor Brand String: Intel(R)Core(TM)i7-7820XCPU@3.60GHz
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX AVX2 AVX-512 F
It's safe to use the following AVX-512 extensions with this machine:
--------------------------------------------------------------------
AVX-512 DQ : Vector Double Word and Quad Word
AVX-512 CD : Efficient conflict detection to allow more loops to be vectorized.
AVX-512 BW : Extends AVX-512 to cover 8-bit and 16-bit integer operations.
AVX-512 VL : Extends most AVX-512 operations to also operate on XMM and YMM registers.
Any processor that implements any portion of the AVX-512 extensions MUST implement AVX-512 F.
Not every architecture has all the instruction sets built in. We've for example:
Knights Landing : CD ER PF
Knights Mill : CD ER PF 4FMAPS 4VNNIW VPOPCNTDQ
Skylake : CD VL DQ BW
Cannon Lake : CD VL DQ BW IFMA VBMI
Cascade Lake : CD VL DQ BW VNNI
Ice Lake : CD VL DQ BW IFMA VBMI VBMI2 VPOPCNTDQ BITALG VNNI VPCLMULQDQ GFNI VAES
Tiger Lake : CD VL DQ BW IFMA VBMI VBMI2 VPOPCNTDQ BITALG VNNI VPCLMULQDQ GFNI VAES VP2INTERSECT
GFNI (Galois Field Affine Transformation), VPCLMULQDQ, and VAES are not AVX-512 features per se.
Together with AVX-512, they enable EVEX encoded versions of GFNI, PCLMULQDQ, and AES instructions.
Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------
RDRAND : Returning random numbers from an on-chip hardware random number generator.
RDSEED : Loads a hardware generated random value and store it in the destination register.
AESNI : Advanced Encryption Standard Instruction Set
VMX : Virtual Machine Extensions
FPU : Floating Point Unit on chip
VME : Virtual 8086 Mode Enhancements
DE : Debugging Extensions. Support for I/O breakpoints.
PSE : Page Size Extension
TSC : Time Stamp Counter. The RDTSC instruction is supported.
MSR : Model Specific Registers RDMSR and WRMSR Instructions.
PAE : Physical Address Extension
CX8 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is supported.
APIC : Processor contains an Advanced Programmable Interrupt Controller (APIC) on board.
Test results on as many different machines as possible are very welcome. Thank you.
Gunther
Gunther,
This is your new one.
CPU strings:
------------
Processor Vendor String: GenuineIntel
Processor Brand String: Intel(R)Xeon(R)CPUE5-2690v3@2.60GHz
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX AVX2
Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------
RDRAND : Returning random numbers from an on-chip hardware random number generator.
RDSEED : Loads a hardware generated random value and store it in the destination register.
AESNI : Advanced Encryption Standard Instruction Set
VMX : Virtual Machine Extensions
SMX : Safer Mode Extensions
FPU : Floating Point Unit on chip
VME : Virtual 8086 Mode Enhancements
DE : Debugging Extensions. Support for I/O breakpoints.
PSE : Page Size Extension
TSC : Time Stamp Counter. The RDTSC instruction is supported.
MSR : Model Specific Registers RDMSR and WRMSR Instructions.
PAE : Physical Address Extension
CX8 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is supported.
APIC : Processor contains an Advanced Programmable Interrupt Controller (APIC) on board.
Just one suggestion,
Processor Brand String: Intel(R)Xeon(R)CPU E5-2690v3@2.60 GHz
Separate the CPI ID by a space, makes it easier to read.
This is off my old i7 5820k clocked at 4 gig.
CPU strings:
------------
Processor Vendor String: GenuineIntel
Processor Brand String: Intel(R)Core(TM)i7-5820KCPU@3.30GHz
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX AVX2
Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------
RDRAND : Returning random numbers from an on-chip hardware random number generator.
RDSEED : Loads a hardware generated random value and store it in the destination register.
AESNI : Advanced Encryption Standard Instruction Set
VMX : Virtual Machine Extensions
FPU : Floating Point Unit on chip
VME : Virtual 8086 Mode Enhancements
DE : Debugging Extensions. Support for I/O breakpoints.
PSE : Page Size Extension
TSC : Time Stamp Counter. The RDTSC instruction is supported.
MSR : Model Specific Registers RDMSR and WRMSR Instructions.
PAE : Physical Address Extension
CX8 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is supported.
APIC : Processor contains an Advanced Programmable Interrupt Controller (APIC) on board.
Hi,
The two laptops again.
CPU strings:
------------
Processor Vendor String: GenuineIntel
Processor Brand String: Intel(R)Core(TM)i3-4005UCPU@1.70GHz
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX AVX2
Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------
RDRAND : Returning random numbers from an on-chip hardware random number generator.
RDSEED : Loads a hardware generated random value and store it in the destination register.
AESNI : Advanced Encryption Standard Instruction Set
VMX : Virtual Machine Extensions
FPU : Floating Point Unit on chip
VME : Virtual 8086 Mode Enhancements
DE : Debugging Extensions. Support for I/O breakpoints.
PSE : Page Size Extension
TSC : Time Stamp Counter. The RDTSC instruction is supported.
MSR : Model Specific Registers RDMSR and WRMSR Instructions.
PAE : Physical Address Extension
CX8 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is supported.
APIC : Processor contains an Advanced Programmable Interrupt Controller (APIC) on board.
Press any key to continue...
CPU strings:
------------
Processor Vendor String: GenuineIntel
Processor Brand String: Intel(R)Core(TM)i3-10110UCPU@2.10GHz
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX AVX2
Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------
RDRAND : Returning random numbers from an on-chip hardware random number generator.
RDSEED : Loads a hardware generated random value and store it in the destination register.
AESNI : Advanced Encryption Standard Instruction Set
VMX : Virtual Machine Extensions
FPU : Floating Point Unit on chip
VME : Virtual 8086 Mode Enhancements
DE : Debugging Extensions. Support for I/O breakpoints.
PSE : Page Size Extension
TSC : Time Stamp Counter. The RDTSC instruction is supported.
MSR : Model Specific Registers RDMSR and WRMSR Instructions.
PAE : Physical Address Extension
CX8 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is supported.
APIC : Processor contains an Advanced Programmable Interrupt Controller (APIC) on board.
Cheers,
Steve N.
My special thanks to Steve and FORTRANS for getting it done really promptly. :thumbsup:
Gunther
Quote from: Gunther on February 05, 2021, 02:18:05 PM
My thanks to mikeburr and Greenhorn for the test results.
Quote from: Greenhorn on February 05, 2021, 09:47:57 AM
Another AMD ...
Why not? It is supposed to be quite a decent processor.
Oh yes, it definitely is !
CpuNew output:
CPU strings:
------------
Processor Vendor String: AuthenticAMD
Processor Brand String: AMDRyzen73700X8-CoreProcessor
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX AVX2
Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------
RDRAND : Returning random numbers from an on-chip hardware random number generator.
AESNI : Advanced Encryption Standard Instruction Set
FPU : Floating Point Unit on chip
VME : Virtual 8086 Mode Enhancements
DE : Debugging Extensions. Support for I/O breakpoints.
PSE : Page Size Extension
TSC : Time Stamp Counter. The RDTSC instruction is supported.
MSR : Model Specific Registers RDMSR and WRMSR Instructions.
PAE : Physical Address Extension
CX8 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is supported.
APIC : Processor contains an Advanced Programmable Interrupt Controller (APIC) on board.
Kind regards
Greenhorn
CPU strings:
------------
Processor Vendor String: AuthenticAMD
Processor Brand String: AMDA6-9220eRADEONR4,5COMPUTECORES2C+3G
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX AVX2
Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------
RDRAND : Returning random numbers from an on-chip hardware random number generator.
AESNI : Advanced Encryption Standard Instruction Set
FPU : Floating Point Unit on chip
VME : Virtual 8086 Mode Enhancements
DE : Debugging Extensions. Support for I/O breakpoints.
PSE : Page Size Extension
TSC : Time Stamp Counter. The RDTSC instruction is supported.
MSR : Model Specific Registers RDMSR and WRMSR Instructions.
PAE : Physical Address Extension
CX8 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is supported.
APIC : Processor contains an Advanced Programmable Interrupt Controller (APIC) on board.
Press any key to continue...
Results of cpuNew1: :thumbsup:
Microsoft Windows [Version 10.0.19041.746]
(c) 2020 Microsoft Corporation. Alle Rechte vorbehalten.
CPU strings:
------------
Processor Vendor String: GenuineIntel
Processor Brand String: Intel(R)Core(TM)i7-4770KCPU@3.50GHz
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX AVX2
Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------
RDRAND : Returning random numbers from an on-chip hardware random number generator.
RDSEED : Loads a hardware generated random value and store it in the destination register.
AESNI : Advanced Encryption Standard Instruction Set
VMX : Virtual Machine Extensions
FPU : Floating Point Unit on chip
VME : Virtual 8086 Mode Enhancements
DE : Debugging Extensions. Support for I/O breakpoints.
PSE : Page Size Extension
TSC : Time Stamp Counter. The RDTSC instruction is supported.
MSR : Model Specific Registers RDMSR and WRMSR Instructions.
PAE : Physical Address Extension
CX8 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is supported.
APIC : Processor contains an Advanced Programmable Interrupt Controller (APIC) on board.
Biterider
Thanks go to Greenhorn, quarantined (another AMD processor :thumbsup:), and Biterider.
Biterider,
Quote from: Biterider on February 07, 2021, 06:01:39 PM
Results of cpuNew1: :thumbsup:
For a standalone assembly language program this could of course be solved more elegantly. The individual procedures are written in such a way that they can be called with small changes from C++.
Each instruction set can then be checked from the high-level language via a variable during runtime. I added this to the C++ program yesterday and it seems to work. The moment of truth will come
when the program is run in Geneva at CERN. We will see. As we all know, the devil is in the details.
Gunther
put original test and latest test through a diff
the only difference is that APIC now begins "Processor" rather than "The processor ...
regards mikeb
Mike,
Quote from: mikeburr on February 11, 2021, 12:29:39 AM
put original test and latest test through a diff
the only difference is that APIC now begins "Processor" rather than "The processor ...
regards mikeb
this should also be the case. Thank you.
Gunther
Msdn sample https://docs.microsoft.com/en-us/cpp/intrinsics/cpuid-cpuidex?view=msvc-160 (https://docs.microsoft.com/en-us/cpp/intrinsics/cpuid-cpuidex?view=msvc-160)
exe with attachment
Thank you Yves.
Gunther
Quote from: Gunther on February 05, 2021, 09:03:53 PM
As promised, here is the revised version of CPU. The new archive is called cpuNew1.zip and is under the first post of this thread.
I fixed some small bugs, reduced the number of procedure calls, and the application tests for more instructions and features. Here is the output on my large machine.
Quote
CPU strings:
------------
Processor Vendor String: GenuineIntel
Processor Brand String: Intel(R)Core(TM)i7-7820XCPU@3.60GHz
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX AVX2 AVX-512 F
It's safe to use the following AVX-512 extensions with this machine:
--------------------------------------------------------------------
AVX-512 DQ : Vector Double Word and Quad Word
AVX-512 CD : Efficient conflict detection to allow more loops to be vectorized.
AVX-512 BW : Extends AVX-512 to cover 8-bit and 16-bit integer operations.
AVX-512 VL : Extends most AVX-512 operations to also operate on XMM and YMM registers.
Any processor that implements any portion of the AVX-512 extensions MUST implement AVX-512 F.
Not every architecture has all the instruction sets built in. We've for example:
Knights Landing : CD ER PF
Knights Mill : CD ER PF 4FMAPS 4VNNIW VPOPCNTDQ
Skylake : CD VL DQ BW
Cannon Lake : CD VL DQ BW IFMA VBMI
Cascade Lake : CD VL DQ BW VNNI
Ice Lake : CD VL DQ BW IFMA VBMI VBMI2 VPOPCNTDQ BITALG VNNI VPCLMULQDQ GFNI VAES
Tiger Lake : CD VL DQ BW IFMA VBMI VBMI2 VPOPCNTDQ BITALG VNNI VPCLMULQDQ GFNI VAES VP2INTERSECT
GFNI (Galois Field Affine Transformation), VPCLMULQDQ, and VAES are not AVX-512 features per se.
Together with AVX-512, they enable EVEX encoded versions of GFNI, PCLMULQDQ, and AES instructions.
Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------
RDRAND : Returning random numbers from an on-chip hardware random number generator.
RDSEED : Loads a hardware generated random value and store it in the destination register.
AESNI : Advanced Encryption Standard Instruction Set
VMX : Virtual Machine Extensions
FPU : Floating Point Unit on chip
VME : Virtual 8086 Mode Enhancements
DE : Debugging Extensions. Support for I/O breakpoints.
PSE : Page Size Extension
TSC : Time Stamp Counter. The RDTSC instruction is supported.
MSR : Model Specific Registers RDMSR and WRMSR Instructions.
PAE : Physical Address Extension
CX8 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is supported.
APIC : Processor contains an Advanced Programmable Interrupt Controller (APIC) on board.
Test results on as many different machines as possible are very welcome. Thank you.
Gunther
Hi Gunther,
AVX-512 is not detected on the new version :tongue:
CPU strings:
------------
Processor Vendor String: GenuineIntel
Processor Brand String: 11thGenIntel(R)Core(TM)i7-11800H@2.30GHz
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX AVX2
Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------
RDRAND : Returning random numbers from an on-chip hardware random number generator.
RDSEED : Loads a hardware generated random value and store it in the destination register.
AESNI : Advanced Encryption Standard Instruction Set
VMX : Virtual Machine Extensions
FPU : Floating Point Unit on chip
VME : Virtual 8086 Mode Enhancements
DE : Debugging Extensions. Support for I/O breakpoints.
PSE : Page Size Extension
TSC : Time Stamp Counter. The RDTSC instruction is supported.
MSR : Model Specific Registers RDMSR and WRMSR Instructions.
PAE : Physical Address Extension
CX8 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is supported.
APIC : Processor contains an Advanced Programmable Interrupt Controller (APIC) on board.
Press any key to continue...
Quote from: LiaoMi on August 14, 2022, 02:56:24 AM
AVX-512 is not detected on the new version :tongue:
I see. But it works fine with my Skylake.
CPU strings:
------------
Processor Vendor String: GenuineIntel
Processor Brand String: Intel(R)Core(TM)i7-7820XCPU@3.60GHz
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX AVX2 AVX-512 F
It's safe to use the following AVX-512 extensions with this machine:
--------------------------------------------------------------------
AVX-512 DQ : Vector Double Word and Quad Word
AVX-512 CD : Efficient conflict detection to allow more loops to be vectorized.
AVX-512 BW : Extends AVX-512 to cover 8-bit and 16-bit integer operations.
AVX-512 VL : Extends most AVX-512 operations to also operate on XMM and YMM registers.[
Do you have any guesses as to where the problem lies? The Iset procedure works exactly according to Intel's recommendations. Nevertheless, I will analyze this again in the next few days.
Have you tested the old version as well?
Hi Gunther,
Quote from: Gunther on August 14, 2022, 07:51:16 PM
Quote from: LiaoMi on August 14, 2022, 02:56:24 AM
AVX-512 is not detected on the new version :tongue:
I see. But it works fine with my Skylake.
CPU strings:
------------
Processor Vendor String: GenuineIntel
Processor Brand String: Intel(R)Core(TM)i7-7820XCPU@3.60GHz
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX AVX2 AVX-512 F
It's safe to use the following AVX-512 extensions with this machine:
--------------------------------------------------------------------
AVX-512 DQ : Vector Double Word and Quad Word
AVX-512 CD : Efficient conflict detection to allow more loops to be vectorized.
AVX-512 BW : Extends AVX-512 to cover 8-bit and 16-bit integer operations.
AVX-512 VL : Extends most AVX-512 operations to also operate on XMM and YMM registers.[
Do you have any guesses as to where the problem lies? The Iset procedure works exactly according to Intel's recommendations. Nevertheless, I will analyze this again in the next few days.
Have you tested the old version as well?
on the last check, the transition to AVX-512 does not work, I have rax = 0Dh
.text:00000001400011A6 loc_1400011A6:
.text:00000001400011A6 cmp rax, 0Dh
.text:00000001400011AA jnz short loc_1400011C1then there is a jump to this code :arrow_down:
.text:00000001400011AC lea rcx, Format
.text:00000001400011B3 lea rdx, aMmxSseSse2Sse3_4 ;
.text:00000001400011BA call sub_140001C95
.text:00000001400011BF jmp short loc_1400011DAThe old version produces the same result :rolleyes:
From my (estimated) 10+ year old box...
CPU strings:
------------
Processor Vendor String: GenuineIntel
Processor Brand String: Intel(R)Core(TM)2DuoCPUE8400@3.00GHz
Features by Processor and Operating System:
-------------------------------------------
Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1
Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------
VMX : Virtual Machine Extensions
SMX : Safer Mode Extensions
FPU : Floating Point Unit on chip
VME : Virtual 8086 Mode Enhancements
DE : Debugging Extensions. Support for I/O breakpoints.
PSE : Page Size Extension
TSC : Time Stamp Counter. The RDTSC instruction is supported.
MSR : Model Specific Registers RDMSR and WRMSR Instructions.
PAE : Physical Address Extension
CX8 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is su
pported.
APIC : Processor contains an Advanced Programmable Interrupt Cont
roller (APIC) on board.
Press any key to continue...
Quote from: zedd151 on August 22, 2022, 05:21:08 AM
From my (estimated) 10+ year old box...
Thanks for your test. :thumbsup: However, the problem is with the AVX-512 detection.
Quote from: Gunther on August 22, 2022, 11:50:28 AM
Thanks for your test. :thumbsup: However, the problem is with the AVX-512 detection.
Test was a success then. Now I know I don't have it. :biggrin:
Hi Gunther!
I added check of bit 12 for FMA to obtain:Supported Instruction Sets: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX AVX2 FMA
I don't know if that way is correct.
Thanks, HSE
HSE,
Quote from: HSE on February 17, 2023, 01:41:02 AM
I don't know if that way is correct.
I don't know at the moment either. But as well as I find time next week, I will have a look. But already now a thank you to you. :thumbsup:
:thumbsup: