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tpause instruction not working

Started by InfiniteLoop, December 12, 2022, 08:49:59 AM

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InfiniteLoop

Greetings,

I have discovered a lightweight problem this time.

According to the manual, tpause should wait for the specified amount of edx:eax cycles, however, it doesn't work. It behaves exactly the same in Windows and in a UEFI program.

Why isn't it working?



; Find max for tpause
ASM_Pause proc
mov ecx,1
lfence
rdtsc
mov r9d,edx
mov r8d,eax
lfence
add eax,3600000000
adc edx,0 ;add roughly 1 second
tpause ecx ;edx:eax
lfence
rdtsc
lfence
jc Max_Limit
shl rdx,32
add rax,rdx
shl r9,32
add r9,r8
sub rax,r9
ret
Max_Limit:
xor eax,eax
ret
ASM_Pause endp

HSE

You have to check this:
QuoteTPAUSE is available when CPUID.7.0:ECX.WAITPKG[bit 5] is enumerated as 1.
Equations in Assembly: SmplMath

InfiniteLoop

It is done. I don't think its the MSR register either since the default is unlimited and the carry flag is never set.

; Find max for tpause
ASM_Pause proc
push rbx
mov eax, 7
xor ecx,ecx
cpuid
and ecx,100000b ;PKG
jz Something_Wrong
mov ecx,1
lfence
rdtsc
mov r9d,edx
mov r8d,eax
lfence
add eax,3600000000
adc edx,0 ;add roughly 1 second
tpause ecx ;edx:eax
jc Something_Wrong
lfence
rdtsc
lfence

shl rdx,32
add rax,rdx
shl r9,32
add r9,r8
sub rax,r9
pop rbx
ret
Something_Wrong:
xor eax,eax
pop rbx
ret
ASM_Pause endp

jj2007

Released in 2020.

QuoteTremont introduced a number of new instructions:

CLWB - Force cache line write-back without flush
ENCLV - SGX oversubscription instructions
CLDEMOTE - Cache line demote instruction
SSE_GFNI - SSE-based Galois Field New Instructions
Direct store instructions: MOVDIRI, MOVDIR64B
User wait instructions: TPAUSE, UMONITOR, UMWAIT
Split Lock Detection - detection and cause an exception for split locks