Dang,...JOCHEN,...
That IS a brilliant idea,...

...Apparently it's a big Windows secret,...
I remember reading something about this years ago (and, unfortunately, I have forgotten all the juicy stuff by now) when I was trying to understand the concept behind the 'Call Gate descriptors' that activate kernel mode threads (when signaled from user mode), to complete the Operating System data storage and processing for the vast majority of Windows APIs (that have any kind of managerial function),...
Here is a GOOGLE search:
global descriptor table register (GDTR)...And, of course,...the definitive Wikipedia page:
Global Descriptor Table, Wikipedia2.7.1 Loading and Storing System Registers
The GDTR, LDTR, IDTR, and TR registers each have a load and store instruction for loading data into and storing data from the register:
• LGDT (Load GDTR Register) — Loads the GDT base address and limit from memory into the GDTR register.
• SGDT (Store GDTR Register) — Stores the GDT base address and limit from the GDTR register into memory.
• LIDT (Load IDTR Register) — Loads the IDT base address and limit from memory into the IDTR register.
• SIDT (Load IDTR Register — Stores the IDT base address and limit from the IDTR register into memory.
• LLDT (Load LDT Register) — Loads the LDT segment selector and segment descriptor from memory into the LDTR. (The segment selector operand can also be located in a general-purpose register.)
• SLDT (Store LDT Register) — Stores the LDT segment selector from the LDTR register into memory or a general-purpose register.
• LTR (Load Task Register) — Loads segment selector and segment descriptor for a TSS from memory into the task register. (The segment selector operand can also be located in a general-purpose register.)
• STR (Store Task Register) — Stores the segment selector for the current task TSS from the task register into memory or a general-purpose register.
The LMSW (load machine status word) and SMSW (store machine status word) instructions operate on bits 0 through 15 of control register CR0. These instructions are provided for compatibility with the 16-bit Intel 286 processor. Programs written to run on 32-bit IA-32 processors should not use these instructions. Instead, they should access the control register CR0 using the MOV instruction.
The CLTS (clear TS flag in CR0) instruction is provided for use in handling a device-not-available exception (#NM) that occurs when the processor attempts to execute a floating-point instruction when the TS flag is set. This instruction allows the TS flag to be cleared after the x87 FPU context has been saved, preventing further #NM exceptions. See Section 2.5, “Control Registers,” for more information on the TS flag.
The control registers (CR0, CR1, CR2, CR3, CR4, and CR8) are loaded using the MOV instruction. The instruction loads a control register from a general-purpose register or stores the content of a control register in a general purpose register.
...The really unfortunate aspect of this entire line of reasoning is that:
you can only call these instructions from KERNEL MODE,...(Ha,...ha,...)
...However,...if you must pursue this subject further, here are a couple of links:
Global Descriptor Table (GDT) Tutorial, OSDev,...and,...
Global Descriptor Table, OSDev,...
...And,...if you just want to get lost in the OS DEV site (
WARNING: You may never come back):
Expanded Main Page, Welcome to OSDev.org
...Of course,...there is a 'high probability' that I could be wrong about all of this stuff,...

...I'll bet
QWORD knows all about this topic,...maybe, if I just make another inane '
MASM Compiler' post, he'll post just to let us know how completely misguided we are,...