Author Topic: Code location sensitivity of timings  (Read 41609 times)

Gunther

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Re: Code location sensitivity of timings
« Reply #75 on: August 19, 2014, 05:08:29 AM »
Jochen,

your timings:
Code: [Select]
Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz (SSE4)

21892   cycles for 100 * memchr scasb
3007    cycles for 100 * memchr SSE2 lps/hps
2690    cycles for 100 * memchr SSE2 nidud
2500    cycles for 100 * memchr SSE2 ups

21951   cycles for 100 * memchr scasb
2981    cycles for 100 * memchr SSE2 lps/hps
2721    cycles for 100 * memchr SSE2 nidud
6211    cycles for 100 * memchr SSE2 ups

21827   cycles for 100 * memchr scasb
3003    cycles for 100 * memchr SSE2 lps/hps
2510    cycles for 100 * memchr SSE2 nidud
2721    cycles for 100 * memchr SSE2 ups

36      bytes for memchr scasb
88      bytes for memchr SSE2 lps/hps
92      bytes for memchr SSE2 nidud
84      bytes for memchr SSE2 ups

--- ok ---

Gunther
You have to know the facts before you can distort them.

nidud

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Re: Code location sensitivity of timings
« Reply #76 on: March 22, 2015, 02:17:44 AM »
deleted
« Last Edit: February 25, 2022, 08:33:12 AM by nidud »