Btw...Someone ever used Agner´sFog pcmtest file on XP (32 bits) bfore ?
I can´t run startcounter here. Neither i can compile the main file. All i was able to compile was the textB App. :( But i´m unable to understand the complete functionality
What exactly is this?
SCounterDefinition CounterDefinitions[] = {
// id scheme cpu countregs eventreg event mask name
{100, S_P4, PRALL, 4, 7, 0, 9, 7, "Uops" }, // uops from any source
{101, S_P4, PRALL, 4, 7, 0, 9, 2, "UopsTC" }, // uops from trace cache
{102, S_P4, PRALL, 4, 7, 0, 9, 1, "UopsDec" }, // uops directly from decoder
{103, S_P4, PRALL, 4, 7, 0, 9, 4, "UopsMCode"}, // uops from microcode ROM
{110, S_P4, PRALL, 12, 17, 4, 1, 1, "UopsNB" }, // uops non-bogus
{111, S_P4, PRALL, 12, 17, 4, 2, 0x0c, "UopsBogus"}, // uops bogus
{150, S_P4, PRALL, 8, 11, 1, 4, 0x8000, "UopsFP" }, // uops floating point, except move etc.
{151, S_P4, PRALL, 8, 11, 1, 0x2e, 8, "UopsFPMov"}, // uops floating point and SIMD move
{152, S_P4, PRALL, 8, 11, 1, 0x2e, 0x10, "UopsFPLd" }, // uops floating point and SIMD load
{160, S_P4, PRALL, 8, 11, 1, 2, 0x8000, "UopsMMX" }, // uops 64-bit MMX
{170, S_P4, PRALL, 8, 11, 1, 0x1a, 0x8000, "UopsXMM" }, // uops 128-bit integer XMM
{200, S_P4, PRALL, 12, 17, 5, 6, 0x0f, "Branch" }, // branches
{201, S_P4, PRALL, 12, 17, 5, 6, 0x0c, "BrTaken" }, // branches taken
{202, S_P4, PRALL, 12, 17, 5, 6, 0x03, "BrNTaken" }, // branches not taken
{203, S_P4, PRALL, 12, 17, 5, 6, 0x05, "BrPredict"}, // branches predicted
{204, S_P4, PRALL, 12, 17, 4, 3, 0x01, "BrMispred"}, // branches mispredicted
{210, S_P4, PRALL, 4, 7, 2, 5, 0x02, "CondJMisp"}, // conditional jumps mispredicted
{211, S_P4, PRALL, 4, 7, 2, 5, 0x04, "CallMisp" }, // indirect call mispredicted
{212, S_P4, PRALL, 4, 7, 2, 5, 0x08, "RetMisp" }, // return mispredicted
{220, S_P4, PRALL, 4, 7, 2, 5, 0x10, "IndirMisp"}, // indirect calls, jumps and returns mispredicted
{310, S_P4, PRALL, 0, 3, 0, 3, 0x01, "TCMiss" }, // trace cache miss
{320, S_P4, PRALL, 0, 3, 7, 0x0c, 0x100, "Cach2Miss"}, // level 2 cache miss
{321, S_P4, PRALL, 0, 3, 7, 0x0c, 0x200, "Cach3Miss"}, // level 3 cache miss
{330, S_P4, PRALL, 0, 3, 3, 0x18, 0x02, "ITLBMiss" }, // instructions TLB Miss
{340, S_P4, PRALL, 0, 3, 2, 3, 0x3a, "LdReplay" }, // memory load replay
// id scheme cpu countregs eventreg event mask name
{ 9, S_P1, PRALL, 0, 1, 0, 0x16, 2, "Instruct" }, // instructions executed
{ 11, S_P1, PRALL, 0, 1, 0, 0x17, 2, "InstVpipe"}, // instructions executed in V-pipe
{202, S_P1, PRALL, 0, 1, 0, 0x15, 2, "Flush" }, // pipeline flush due to branch misprediction or serializing event
{310, S_P1, PRALL, 0, 1, 0, 0x0e, 2, "CodeMiss" }, // code cache miss
{311, S_P1, PRALL, 0, 1, 0, 0x29, 2, "DataMiss" }, // data cache miss
// id scheme cpu countregs eventreg event mask name
{ 9, S_P2MC, PRALL, 0, 1, 0, 0xc0, 0, "Instruct" }, // instructions executed
{ 10, S_P2MC, PRALL, 0, 1, 0, 0xd0, 0, "IDecode" }, // instructions decoded
{ 20, S_P2MC, PRALL, 0, 1, 0, 0x80, 0, "IFetch" }, // instruction fetches
{ 21, S_P2MC, PRALL, 0, 1, 0, 0x86, 0, "IFetchStl"}, // instruction fetch stall
{ 22, S_P2MC, PRALL, 0, 1, 0, 0x87, 0, "ILenStal" }, // instruction length decoder stalls
{100, S_P2MC, INTEL_PM, 0, 1, 0, 0xc2, 0, "Uops(F)" }, // microoperations in fused domain
{100, S_P2MC, PRALL, 0, 1, 0, 0xc2, 0, "Uops" }, // microoperations
{110, S_P2MC, INTEL_PM, 0, 1, 0, 0xa0, 0, "Uops(UF)" }, // unfused microoperations submitted to execution units (Undocumented counter!)
{104, S_P2MC, INTEL_PM, 0, 1, 0, 0xda, 0, "UopsFused"}, // fused uops
{115, S_P2MC, INTEL_PM, 0, 1, 0, 0xd3, 0, "SynchUops"}, // stack synchronization uops
{121, S_P2MC, PRALL, 0, 1, 0, 0xd2, 0, "PartRStl" }, // partial register access stall
{130, S_P2MC, PRALL, 0, 1, 0, 0xa2, 0, "Rs Stall" }, // all resource stalls
{201, S_P2MC, PRALL, 0, 1, 0, 0xc9, 0, "BrTaken" }, // branches taken
{204, S_P2MC, PRALL, 0, 1, 0, 0xc5, 0, "BrMispred"}, // mispredicted branches
{205, S_P2MC, PRALL, 0, 1, 0, 0xe6, 0, "BTBMiss" }, // static branch prediction made
{310, S_P2MC, PRALL, 0, 1, 0, 0x28, 0x0f, "CodeMiss" }, // level 2 cache code fetch
{311, S_P2MC, INTEL_P23,0, 1, 0, 0x29, 0x0f, "L1D Miss" }, // level 2 cache data fetch
(...)
// end of list
{0, S_UNKNOWN, PRUNKNOWN, 0, 0, 0, 0, 0, 0 } // list must end with a record of all 0
};