Author Topic: on-chip random numbers  (Read 1255 times)

Raistlin

  • Member
  • ***
  • Posts: 353
Re: on-chip random numbers
« Reply #15 on: April 17, 2018, 03:21:25 PM »
From what I've read, RdRand is pretty fast (requests in the nanosecond ranges) and reasonably "secure" for cryptographic use.
The compatibility issue however is of more concern for generic implementations. I will be adding its detection to my hardware enumerator/system profiler in any case.

@hutch : https://www.nytimes.com/2013/09/06/us/nsa-foils-much-internet-encryption.html   
<-This is where the NSA tried to alter RdRand to make it less random

Just for interest, anyone worked with hle/rtm (Transactional Synchronization Extensions) CPUID functions (Multi threading) ?
CPUID function 7 -> EBX bits : 4 and 11

Instructions: XACQUIRE,LOCK,XRELEASE,XBEGIN,XEND,XABORT   
Are you pondering what I'm pondering? It's time to take over the world ! - let's use ASSEMBLY...

Raistlin

  • Member
  • ***
  • Posts: 353
Re: on-chip random numbers
« Reply #16 on: April 18, 2018, 03:28:53 PM »
Never-mind - found some more information. Let me share, this looks promising to say the least.

https://www.felixcloutier.com/x86/XACQUIRE:XRELEASE.html  (Hardware Lock Elision) HLE / TSX

https://www.scss.tcd.ie/Jeremy.Jones/CS4021/transactional%20memory.pdf (Restricted Transactional Memory) RTM
Are you pondering what I'm pondering? It's time to take over the world ! - let's use ASSEMBLY...

AW

  • Member
  • *****
  • Posts: 1347
  • Let's Make ASM Great Again!
Re: on-chip random numbers
« Reply #17 on: April 18, 2018, 06:35:06 PM »
Quote
Just for interest, anyone worked with hle/rtm (Transactional Synchronization Extensions) CPUID functions (Multi threading) ?
Probably not, given the amount of zero byte locking files databases continue to spill over.

Raistlin

  • Member
  • ***
  • Posts: 353
Re: on-chip random numbers
« Reply #18 on: April 18, 2018, 07:27:49 PM »
@aw27 - I was thinking of using TSX/HLE for our multi-threaded IOCP servers.
We could potentially eliminate the Critical sections (my case) / Semaphore (your case)
mechanisms that currently steal valuable clock cycles. Seems less clunky as well.
« Last Edit: April 18, 2018, 08:36:37 PM by Raistlin »
Are you pondering what I'm pondering? It's time to take over the world ! - let's use ASSEMBLY...

AW

  • Member
  • *****
  • Posts: 1347
  • Let's Make ASM Great Again!
Re: on-chip random numbers
« Reply #19 on: April 18, 2018, 08:19:10 PM »
You may try, but listen to the silence of Intel....
What I mean is that according to the grapevine and the errata, TSX is not yet free of bugs.

Errata:
https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/desktop-6th-gen-core-family-spec-update.pdf

AW

  • Member
  • *****
  • Posts: 1347
  • Let's Make ASM Great Again!
Re: on-chip random numbers
« Reply #20 on: April 18, 2018, 10:53:49 PM »
In addition, I could not find any processor able to support either RTM or HLE.  :(
I run also the Intel emulator without success.  :(

Code: [Select]
includelib \masm32\lib64\msvcrt.lib
printf PROTO :PTR, :VARARG
includelib \masm32\lib64\kernel32.lib
ExitProcess PROTO :DWORD

.data
nortm db "RTM not supported",10,0
nohle db "HLE not supported",10,0

.code


main proc
sub rsp, 28h
; Are RTM & HLE supported?
mov eax, 7
mov ecx, 0
cpuid
bt ebx, 11
jc hle
mov rcx, offset nortm
call printf
hle:
bt ebx, 4
jc exit; supported
mov rcx, offset nohle
call printf

exit:
mov rcx, 0
call ExitProcess

main endp

end

And MASM does not recognize any of the instructions XACQUIRE,LOCK,XRELEASE,XBEGIN,XEND,XABORT.

So, it is a whole fantasy.

Raistlin

  • Member
  • ***
  • Posts: 353
Re: on-chip random numbers
« Reply #21 on: April 19, 2018, 02:59:15 PM »
D@mn!t  - oh well. That is strange though, TSX/HLE has been around since 2014 (Haswell).
 
Are you pondering what I'm pondering? It's time to take over the world ! - let's use ASSEMBLY...

hutch--

  • Administrator
  • Member
  • ******
  • Posts: 5484
  • Mnemonic Driven API Grinder
    • The MASM32 SDK
Re: on-chip random numbers
« Reply #22 on: April 19, 2018, 05:11:18 PM »
Rudi,

Thanks for the link, its an interesting read and gives you every good reason to avoid anything that is well known in the field of encryption as it is probably compromised before it hits the market. Its the normal response, if the good guys (sic) can use it, the bad guys can as well. Any of the big players already know this and I imagine that any of them already have very big computer grunt for breaking anything that relies on the key bit size.

The stupid part is that anyone who seriously needs to encrypt data is not using crap like this, they are using their own techniques and this goes for fruitcakes like the Islamic State, spies of any of the government agencies, truly big business and folks doing secret research on some massive range of subjects. Security agencies grabbing at information are not doing it for security reasons, they are doing it for control and clandestine theft of technology.
hutch at movsd dot com
http://www.masm32.com    :biggrin:  :biggrin:

AW

  • Member
  • *****
  • Posts: 1347
  • Let's Make ASM Great Again!
Re: on-chip random numbers
« Reply #23 on: April 23, 2018, 07:52:52 PM »
D@mn!t  - oh well. That is strange though, TSX/HLE has been around since 2014 (Haswell).
Oh yeah, d@mn!t:
https://www.youtube.com/watch?v=AIXUgtNC4Kc

Raistlin

  • Member
  • ***
  • Posts: 353
Re: on-chip random numbers
« Reply #24 on: April 24, 2018, 03:01:03 PM »
 :greenclp:
Are you pondering what I'm pondering? It's time to take over the world ! - let's use ASSEMBLY...

K_F

  • Member
  • *****
  • Posts: 1377
  • Anybody out there?
Re: on-chip random numbers
« Reply #25 on: April 27, 2018, 08:32:03 PM »
Oh yeah, d@mn!t:
https://www.youtube.com/watch?v=AIXUgtNC4Kc
So sad.. but that's representative of the state that SA has descended to..  :lol:
'Sire, Sire!... the peasants are Revolting !!!'
'Yes, they are.. aren't they....'

AW

  • Member
  • *****
  • Posts: 1347
  • Let's Make ASM Great Again!
Re: on-chip random numbers
« Reply #26 on: April 27, 2018, 10:27:59 PM »
It is difficult for Raistlin to do TSX/HLE assembly language in there.  :(

zedd151

  • Member
  • ****
  • Posts: 703
Re: on-chip random numbers
« Reply #27 on: May 07, 2018, 03:12:59 AM »

....Try this one out on your computer, it test if RDRAND is available and if it is, it runs it.


Code: [Select]
Entropy = 7.999998 bits per byte.

Optimum compression would reduce the size
of this 80000000 byte file by 0 percent.

Chi square distribution for 80000000 samples is 232.44, and randomly
would exceed this value 75.00 percent of the times.

Arithmetic mean value of data bytes is 127.5112 (127.5 = random).
Monte Carlo value for Pi is 3.140695879 (error 0.03 percent).
Serial correlation coefficient is 0.000011 (totally uncorrelated = 0.0).

That's all folks
Press any key to exit ....

Processor   AMD A6-9220e RADEON R4, 5 COMPUTE CORES 2C+3G, 1600 Mhz, 2 Core(s), 2 Logical Processor(s)    :biggrin:


AW

  • Member
  • *****
  • Posts: 1347
  • Let's Make ASM Great Again!
Re: on-chip random numbers
« Reply #28 on: May 13, 2018, 01:25:04 AM »
After scratching my head looking for the reasons the Intel emulator does not properly identify TSX instructions I found that the answer lies in a mysterious switch that we only know about in the extended help.
So, if I do: "sde -help" in the command line, nothing surfaces about TSX. But if I do "sde -long-help" it is all there.

Now, if I have a file called tsx.exe with TSX instructions, I can make the emulator run as if it had an Haswell CPU (before TSX being disabled in the Haswell CPU  :lol: ). Well, it appears that in real life, TSX instructions are currently disabled in all recent CPUs, except some server models, but someday all will be back to normal and we all will be more happy with those TSX instructions.

This is my reviewed TSX identification snippet, tested on the emulator.

Code: [Select]

includelib \masm32\lib64\msvcrt.lib
printf PROTO :PTR, :VARARG
includelib \masm32\lib64\kernel32.lib
ExitProcess PROTO :DWORD

.data
nortm db "RTM not supported",10,0
rtm db "RTM supported",10,0
nohle db "HLE not supported",10,0
hle db "HLE supported",10,0

.code

main proc
sub rsp, 28h
; Are RTM & HLE supported?
mov eax, 7
mov ecx, 0
cpuid
bt ebx, 11
jc rtmsup
mov rcx, offset nortm
call printf
jmp short skiprtmsup
rtmsup:
mov rcx, offset rtm
call printf
skiprtmsup:
bt ebx, 4
jc hlesup
mov rcx, offset nohle
call printf
jmp short exit
hlesup:
mov rcx, offset hle
call printf

exit:
mov rcx, 0
call ExitProcess

main endp

end

I was also badmouthing MASM for not recognizing any of the instructions XACQUIRE,LOCK,XRELEASE,XBEGIN,XEND,XABORT. Actually, it does recognize, I was not using the correct syntax.




felipe

  • Member
  • ****
  • Posts: 867
  • Eagles are just great!
Re: on-chip random numbers
« Reply #29 on: May 13, 2018, 01:09:37 PM »
Nice program aw27, i like your style, thanks for sharing:

Code: [Select]
C:\masm32\xxx>xxx
RTM not supported
HLE not supported

C:\masm32\xxx>

 :icon14:
Felipe.