Author Topic: Conditional Assembly based on CPU bitness  (Read 242 times)

AW

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Conditional Assembly based on CPU bitness
« on: February 26, 2019, 06:24:09 PM »
This is a challenge!
In MASM, how to automatically detect architecture at assembly time?
For example:
How to set size_t to either dword or qword according to assembly with ml.exe or ml64.exe
myfunc proto :ptr, :ptr, :size_t

Adamanteus

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Re: Conditional Assembly based on CPU bitness
« Reply #1 on: February 26, 2019, 11:06:47 PM »
Somehow this way :
Code: (asm) [Select]
IF @Model eq 7  ; flat model

 if (TYPE NEAR) eq 0FF04h ; 32-bit mode
SIZE_T TEXTEQU <DWORD>
 else
SIZE_T TEXTEQU <QWORD>
 endif

INT_T TEXTEQU <DWORD>
 
ELSE    ; other models

 IF @DataSize
SIZE_T TEXTEQU <DWORD>
 ELSE
SIZE_T TEXTEQU <WORD>
 ENDIF

INT_T TEXTEQU <WORD>
 
ENDIF

nidud

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Re: Conditional Assembly based on CPU bitness
« Reply #2 on: February 27, 2019, 12:00:16 AM »
size_t typedef ptr

LiaoMi

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Re: Conditional Assembly based on CPU bitness
« Reply #3 on: February 27, 2019, 01:14:14 AM »
Somehow this way :
Code: (asm) [Select]
IF @Model eq 7  ; flat model

 if (TYPE NEAR) eq 0FF04h ; 32-bit mode
SIZE_T TEXTEQU <DWORD>
 else
SIZE_T TEXTEQU <QWORD>
 endif

INT_T TEXTEQU <DWORD>
 
ELSE    ; other models

 IF @DataSize
SIZE_T TEXTEQU <DWORD>
 ELSE
SIZE_T TEXTEQU <WORD>
 ENDIF

INT_T TEXTEQU <WORD>
 
ENDIF

error A2006:undefined symbol : @DataSize
error A2006:undefined symbol : @Model

Code: [Select]
@WordSize: The @WordSize text macro returns the word size of the segment word size in bytes. It returns 4 when the word size is 32 bits and 2 when the word size is 16 bits. By default, the segment word size is 16 bits with the 80286 and other 16-bit processors, and 32 bits with the 80386.
@Cpu: The @Cpu text macro returns a 16-bit value containing information about the selected processor. You select a processor by using one of the processor directives such as the .286 directive. You can use the @Cpu text macro to control assembly of processor-specific code. Individual bits in the value returned by @Cpu indicate information about the selected processor.

these options don't work for me  :(

AW

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Re: Conditional Assembly based on CPU bitness
« Reply #4 on: February 27, 2019, 01:41:55 AM »
Both work very well.
Adamanteus solution appears to require a more modern MASM than the one distributed with the Masm32 SDK. This is strange indeed, because these predefined symbols are mentioned in the MASM manual.
Edited:
It works when we don't forget to select the CPU (.386,.486,...)

Another solution:

ifdef rax ; 64-bit?
   size_t typedef QWORD
else
   size_t typedef DWORD
endif


daydreamer

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Re: Conditional Assembly based on CPU bitness
« Reply #5 on: February 27, 2019, 03:16:58 AM »
Aw i used macros before with redefine with help of nokeyword
Maybe possible to redefine all qword and dword too?
Maybe possible redefine mov rax to mov eax
Research if its same as a prefix between 16bit and 32bit x86, also when i worked with sse2 macros,prefix controlled difference if its mmx and sse : sse2 integer and sse2 doubleprecision, some exceptions the new added opcodes
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