Author Topic: freg: Pseudo push/pop registers in 64 bits  (Read 324 times)

jj2007

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Re: freg: Pseudo push/pop registers in 64 bits
« Reply #15 on: April 03, 2021, 12:11:13 AM »
A good reason to stick to rsp frames is x64 exception handling.

https://docs.microsoft.com/en-us/cpp/build/exception-handling-x64?view=msvc-160
Quote
Frame register

If nonzero, then the function uses a frame pointer (FP), and this field is the number of the nonvolatile register used as the frame pointer, using the same encoding for the operation info field of UNWIND_CODE nodes.

Frame register offset (scaled)

If the frame register field is nonzero, this field is the scaled offset from RSP that is applied to the FP register when it's established. The actual FP register is set to RSP + 16 * this number, allowing offsets from 0 to 240. This offset permits pointing the FP register into the middle of the local stack allocation for dynamic stack frames, allowing better code density through shorter instructions. (That is, more instructions can use the 8-bit signed offset form.)

For timings, see Shadow space in 64-bit programming

P.S.: If anybody knows what exactly they mean with "middle", please tell me, I am curious. It sounds good to have the full range, and a compiler can surely do it, but I can't see how to do it in with current assemblers. Like this maybe?
Code: [Select]
someproc
Local v1
  mov rax, v1[Myoffset]
« Last Edit: April 03, 2021, 01:45:08 AM by jj2007 »

HSE

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Re: freg: Pseudo push/pop registers in 64 bits
« Reply #16 on: April 07, 2021, 03:17:31 AM »
 Hi!

There was a little problem if register is "assumed".

When "assumed", register is saved as dword in 32 bits, or as qword in 64 bits (JWasm family).

Updated in first post.

Regards.

HSE

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Re: freg: Pseudo push/pop registers in 64 bits
« Reply #17 on: April 10, 2021, 01:43:29 AM »
Hi All!

 Added pseudo push/pop of variables (not a lot in my 32 bit code, but there are some). It's a little more tricky because need a GPR to move value (by default are eax and R10 but you can use other):
Code: [Select]
  freg_pushv [xax].SDLL_ITEM.pNextItem, R11
  ยทยทยทยท
  freg_pop xax
 

 Also a not so automatic correction for unbalanced number of push/pop. That happen in conditional flow:
Code: [Select]
  freg_push xax
  .if [xsi].BibBigMaster.options.TextEdition
invoke CheckMenuItem, xax, IDM_TEXT_ED, MF_UNCHECKED
freg_pop xax
invoke CheckMenuItem, xax, IDM_BLOCK_ED, MF_CHECKED
  .else
invoke CheckMenuItem, xax, IDM_TEXT_ED, MF_CHECKED
freg_correction +1
freg_pop xax
invoke CheckMenuItem, xax, IDM_BLOCK_ED, MF_UNCHECKED
  .endif

Uploaded in first post.

Regars, HSE.