IOfinSICB.asm(248) : error A2070: invalid instruction operands
IOfinSICB.asm(251) : error A2070: invalid instruction operands
IOfinSICB.asm(257) : error A2070: invalid instruction operands
I have 450 bit array which I need to test. I defined it as: TabDeComp Byte 58 Dup (0)
the sequence of instruction are the following:
Mov Esi, pFfin2 ; Origen dat
Mov Edi, pMemory
Mov Ebx, 7
LoopDeCmp:
248 Bt TabDeComp, Ebx
Jnc DorQ
Dec Ebx
251 Bt TabDeComp, Ebx
Jc PassBump ; Es Dup
Fldz ; pongo cero
Jmp PassBump
DorQ:
Dec Ebx
257 Bt [TabDeComp], Ebx
Jnc esQW
Fild DWord Ptr [Esi]
Add Esi, 4
Jmp PassBump
esQW:
Fild QWord Ptr [Esi]
Add Esi, 8
PassBump:
Fistp QWord Ptr [Edi]
Add Edi, 8
Bt Ebx, 2 ; Test 7
Jnc LoopDeCmp ; 3 o 1
Bt Ebx, 1
Jnc LoopDeCmp ; 5
Add Ebx, 8
Cmp Ebx, 450
Jl LoopDeCmp
I'm a bit confused with the ERROR as in the Art of Assembly I found
QUOTE:
6.6.4.2 The Bit Test Instructions: BT, BTS, BTR, and BTC
On an 80386 or later processor, you can use the bt instruction (bit test) to test a single bit. Its second operand specifies the bit index into the first operand. Bt copies the addressed bit into the carry flag. For example, the instruction bt ax, 12 copies bit twelve of ax into the carry flag.
The bt/bts/btr/btc instructions only deal with 16 or 32 bit operands. This is not a limitation of the instruction. After all, if you want to test bit three of the al register, you can just as easily test bit three of the ax register. On the other hand, if the index is larger than the size of a register operand, the result is undefined.
If the first operand is a memory location, the bt instruction tests the bit at the given offset in memory, regardless the value of the index. For example, if bx contains 65 then bt TestMe, bx will copy bit one of location TestMe+8 into the carry flag. Once again, the size of the operand does not matter. For all intents and purposes, the memory operand is a byte and you can test any bit after that byte with an appropriate index. The actual bit bt tests is at bit position index mod 8 and at memory offset effective address + index/8.
The bts, btr, and btc instructions also copy the addressed bit into the carry flag. However, these instructions also set, reset (clear), or complement (invert) the bit in the first operand after copying it to the carry flag. This provides test and set, test and clear, and test and invert operations necessary for some concurrent algorithms.
The bt, bts, btr, and btc instructions do not affect any flags other than the carry flag.
UNQUOTE
It would seem that what I'm doing is correct?
I know it can be done throw a series of MOV to registers, but this would defeat my intentions of learning PC assembly and doing it the fastest way possible.
QuoteCode Mnemonic Description
0F A3 BT r/m16, r16 Store selected bit in CF flag
0F A3 BT r/m32, r32 Store selected bit in CF flag
0F BA /4 ib BT r/m16, imm8 Store selected bit in CF flag
0F BA /4 ib BT r/m32, imm8 Store selected bit in CF flag
bt word ptr TabDeComp, 7
bt dword ptr TabDeComp, 7
You need a size override: Bt dword ptr TabDeComp, ebx will work.
Welcome to the forum :icon14:
Thank you both.
It compiles without error either "Bt Word Ptr TabDeComp, Bx" or "Bt Word Ptc [TabDeComp], Bx". My next step will be verify it acts as I need, but that is another story.
Hi alanabbott,
welcome to the forum.
Gunther
Note, if you specify just a register, the code when executed will just set the bit in the register (the input value will be masked to the appropriate size based on the specified register, i.e. AL, AX , EAX ,RAX). If you specify a register pointer, then you are specifying a little endian memory bit string starting at the byte pointed to by the register.
Dave.