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im trying to convert ((0xFF & (__readmsr(0xCE) >> 8)) * 100000000ULL); to masm am i doing correct?

.code
freqreading PROC
        mov rcx, 0CEH
        rdmsr
        shl rdx, 32
        or rax, rdx
        and     rax, 0FF00h
        shr     rax, 8 
        mov     rcx, 100000000
        mul     rcx
        ret                                                       
freqreading ENDP
end

[delete]

Quote from: v0xX on February 17, 2024, 10:23:42 AMam i doing correct?

Looks correct to me, but if you want to be really sure, insert an _asm int 3; into your C or C++ program and let the debugger (e.g. x64 or Olly64 (https://masm32.com/board/index.php?msg=126456)) help you.

No. At least "shr" must be before "and".

Quote from: HSE on February 17, 2024, 12:31:49 PM"shr" must be before "and"

Correct, I didn't see that :thumbsup:

Quote from: HSE on February 17, 2024, 12:31:49 PMNo. At least "shr" must be before "and".

.code
freqreading PROC
        mov     rcx, 0CEH        
        rdmsr                        
        shl     rdx, 32              
        or      rax, rdx             
        shr     rax, 8              
        and     rax, 0FF00h           
        mov     rcx, 100000000
        mul     rcx                  
        ret
freqreading ENDP
end  (https://i.imgur.com/8Bi0yNw.png) 
.code
freqreading PROC
        mov     rcx, 0CEH
        rdmsr
        shl     rdx, 32       
        or      rax, rdx        
        and     rax, 0FF00h     
        shr     rax, 8          
        mov     rcx, 100000000
        mul     rcx
        ret
freqreading ENDP
end
(https://i.imgur.com/qWmKi3T.png) seems return to correctly on 9900ks the original code

msvc
int __cdecl main(void)
{
 __int64 ll = ((0xFF & (__readmsr(0xCE) >> 8)) * 100000000ULL);

return 0;
}
main:
00000000  4883EC18                sub rsp, 18h
00000004  B9CE000000              mov ecx, CEh
00000009  0F32                    rdmsr
0000000B  48C1E220                shl rdx, 20h
0000000F  480BC2                  or rax, rdx
00000012  48C1E808                shr rax, 8h
00000016  4825FF000000            and rax, FFh
0000001C  4869C000E1F505          imul rax, rax, 5F5E100h
00000023  48890424                mov qword ptr [rsp], rax
00000027  33C0                    xor eax, eax
00000029  4883C418                add rsp, 18h
0000002D  C3                      ret
#include <intrin.h>
#include <stdio.h>
int __cdecl main(void)
{
 __int64 ll = ((0xFF & (__readmsr(0xCE) >> 8)) * 100000000ULL);
 printf("%llu\n", ll);
return 0;
}
with Clangmain:
00000000  4883EC28                 sub rsp, 28h
00000004  B9CE000000               mov ecx, CEh
00000009  E800000000               call __readmsr
0000000E  0FB6C4                   movzx eax, ah
00000011  4869D000E1F505           imul rdx, rax, 5F5E100h
00000018  488D0D00000000           lea rcx, [??_C@_05JMLLFKBP@?$CFllu?6?$AA@]
0000001F  E800000000               call printf
00000024  31C0                     xor eax, eax
00000026  4883C428                 add rsp, 28h
0000002A  C3                       ret


Quote from: TimoVJL on February 17, 2024, 09:03:08 PMmsvc

Code Select Expand

int __cdecl main(void)
{
 __int64 ll = ((0xFF & (__readmsr(0xCE) >> 8)) * 100000000ULL);

return 0;
}


Code Select Expand

main:
00000000  4883EC18                sub rsp, 18h
00000004  B9CE000000              mov ecx, CEh
00000009  0F32                    rdmsr
0000000B  48C1E220                shl rdx, 20h
0000000F  480BC2                  or rax, rdx
00000012  48C1E808                shr rax, 8h
00000016  4825FF000000            and rax, FFh
0000001C  4869C000E1F505          imul rax, rax, 5F5E100h
00000023  48890424                mov qword ptr [rsp], rax
00000027  33C0                    xor eax, eax
00000029  4883C418                add rsp, 18h
0000002D  C3                      ret


Code Select Expand

#include <intrin.h>
#include <stdio.h>
int __cdecl main(void)
{
 __int64 ll = ((0xFF & (__readmsr(0xCE) >> 8)) * 100000000ULL);
 printf("%llu\n", ll);
return 0;
}
with Clang

Code Select Expand

main:
00000000  4883EC28                 sub rsp, 28h
00000004  B9CE000000               mov ecx, CEh
00000009  E800000000               call __readmsr
0000000E  0FB6C4                   movzx eax, ah
00000011  4869D000E1F505           imul rdx, rax, 5F5E100h
00000018  488D0D00000000           lea rcx, [??_C@_05JMLLFKBP@?$CFllu?6?$AA@]
0000001F  E800000000               call printf
00000024  31C0                     xor eax, eax
00000026  4883C428                 add rsp, 28h
0000002A  C3                       ret


thank you so much  :cool:

This might be useful:
Compiler Explorer (https://godbolt.org)

"rdmsr" instruction
Reads the contents of a 64-bit model specific register (MSR) specified in the ECX register into registers EDX:EAX.
(On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The EDX register
is loaded with the high-order 32 bits of the MSR and the EAX register is loaded with the low-order 32 bits. (On
processors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are cleared.) If
fewer than 64 bits are implemented in the MSR being read, the values returned to EDX:EAX in unimplemented bit
locations are undefined.
This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection
exception #GP(0) will be generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a
general protection exception.
The MSRs control functions for testability, execution tracing, performance-monitoring, and machine check errors.
Chapter 2, "Model-Specific Registers (MSRs)" of the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 4, lists all the MSRs that can be read with this instruction and their addresses. Note that each
processor family has its own set of MSRs.
The CPUID instruction should be used to determine whether MSRs are supported (CPUID.01H:EDX[5] = 1) before
using this instruction.