For initial acquaintance with the vast diversity of the ISAs, I've written (in Bulgarian) the following article whose machine translation into English can be read here (https://lucho-ddns-net.translate.goog/lig/arch.html?_x_tr_sl=auto&_x_tr_tl=en).
In short, there are no pure CISC and RISC ISAs, but there are some typical features of the RISC concept.
The more RISCy an ISA is, the more of them are present in it.
Typically, what make assembly language programming for the RISC ISAs easier are the three-operand instructions and the larger register count in most RISCs, plus the conditional instructions in some of them.
What make it harder are the impossibility to address the memory by the arithmetic and logical instructions, the typically simpler addressing modes and that some of them have delayed branching and / or lack visible condition code bits.
Probably the best type of architecture for learning how the CPU works is the VLIW, and more specifically a VLIW whose assembler doesn't group the instructions automatically but forces the programmer to do it by hand. Or in other words, all that the non-VLIW CPU does by itself (like instruction reordering and grouping) must be done by the assembly language programmer.
A splendid way to feel like a CPU! :biggrin: