I bothered to extract a full mnemonic list from the current Intel instruction manual for future tasks and while I had a list of 1169 words I plugged it into a high speed word matching algorithm to test how fast this type of code is in 64 bit. The attached file loads the word list then tests each word against the algorithm and repeats the test 200000 times to get a long enough timing. The results on this Haswell I am using is a bit over 55 million word matches a second.
Mnemonic count = 1169
Timing, 233800000 word comparisons in 4328 ms
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You may like the "jump" macro used in the main loop.
; -----------------------------------------------
lpst:
mov r15, arr ; pointer array address
xor r14, r14 ; zero index
mov cntr, 0 ; set counter to 0
@@:
invoke ismnemonic,QWORD PTR [r15+r14] ; call the word matching algo
add r14, 8 ; next pointer array address
add cntr, 1 ; increment the counter
jump @B IF cntr LT lcnt ; loop again if cntr < lcnt
sub r13, 1 ; decrement outer loop counter
jnz lpst
; -----------------------------------------------
Quote from: hutch-- on September 02, 2016, 10:01:33 AM
You may like the "jump" macro used in the main loop
...
jump @B IF cntr LT lcnt ; loop again if cntr < lcnt
Can I claim royalties?
Quote from: jj2007 on May 06, 2016, 09:25:23 AMthe Switch_ macro can now handle lt and gt:
;)
Mnemonic count = 1169
Timing, 233800000 word comparisons in 4203 ms
Press any key to continue...
Mnemonic count = 1169
Timing, 233800000 word comparisons in 4188 ms
Press any key to continue...
Mnemonic count = 1169
Timing, 233800000 word comparisons in 4218 ms
Press any key to continue...
i7-4810mq
:biggrin:
> Can I claim royalties?
Nah, MASM did it first with its 1990 macro engine. Here is a list of the rest. Main reason for these is the incapacity to use < or > on a single line as the macro engine interprets it as an error.
**************************************
variable run time comparison operators
**************************************
-------------
equality test
-------------
eq equal
ne not equal
-----------------
signed comparison
-----------------
gt signed greater than
lt signed less than
ge signed greater than or equal
le signed less than or equal
-------------------
unsigned comparison
-------------------
ua unsigned above
ub unsigned below
ae unsigned above or equal
be unsigned below or equal
**************************************
Quote from: hutch-- on September 02, 2016, 07:39:11 PMthe incapacity to use < or > on a single line
Yes, that was a lousy decision. Even worse, the abuse of the exclamation mark ::)
Assembling: mntest.asm
\masm32\macros64\vasily.inc(996) : error A2154: syntax error in control-flow directive
\masm32\macros64\vasily.inc(996): Included by
\masm32\include64\masm64rt.inc(6): Included by
mntest.asm(3): Main line code
\masm32\macros64\vasily.inc(999) : error A2008: syntax error : J_POLY_COND
\masm32\macros64\vasily.inc(999): Included by
\masm32\include64\masm64rt.inc(6): Included by
mntest.asm(3): Main line code
\masm32\macros64\vasily.inc(1000) : fatal error A1008: unmatched macro nestingLittle compatibility problems ;)
I can live with the macro form of GT, LT etc .... as it allows you to do both signed and unsigned. Vasily uses "{" or "}" as substitutes and it works OK but looks unusual. I have got a number of loop code macros up and going now that use the character pairs rather than the symbols so it is at least consistent.
under wine
Mnemonic count = 1169
Timing, 233800000 word comparisons in 17827 ms
Press any key to continue...
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 15
model name : Intel(R) Pentium(R) Dual CPU E2160 @ 1.80GHz
stepping : 11
microcode : 0xba
cpu MHz : 1200.000
cache size : 1024 KB
physical id : 0
siblings : 2
core id : 0
cpu cores : 2
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 10
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts rep_good nopl aperfmperf pni dtes64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm lahf_lm dtherm
bogomips : 3599.95
clflush size : 64
cache_alignment : 64
address sizes : 36 bits physical, 48 bits virtual
power management: