Test Results for feature detection required

[LiaoMi]

As promised, here is the revised version of CPU. The new archive is called cpuNew1.zip and is under the first post of this thread.

I fixed some small bugs, reduced the number of procedure calls, and the application tests for more instructions and features. Here is the output on my large machine.

CPU strings:
------------

Processor Vendor String: GenuineIntel
Processor Brand String:  Intel(R)Core(TM)i7-7820XCPU@3.60GHz

Features by Processor and Operating System:
-------------------------------------------

Supported Instruction Sets: MMX  SSE  SSE2  SSE3  SSSE3  SSE4.1  SSE4.2  AVX  AVX2  AVX-512 F

It's safe to use the following AVX-512 extensions with this machine:
--------------------------------------------------------------------

AVX-512 DQ          : Vector Double Word and Quad Word
AVX-512 CD          : Efficient conflict detection to allow more loops to be vectorized.
AVX-512 BW          : Extends AVX-512 to cover 8-bit and 16-bit integer operations.
AVX-512 VL          : Extends most AVX-512 operations to also operate on XMM and YMM registers.

Any processor that implements any portion of the AVX-512 extensions MUST implement AVX-512 F.
Not every architecture has all the instruction sets built in. We've for example:

Knights Landing     : CD ER PF
Knights Mill        : CD ER PF 4FMAPS 4VNNIW VPOPCNTDQ
Skylake             : CD VL DQ BW
Cannon Lake         : CD VL DQ BW IFMA VBMI
Cascade Lake        : CD VL DQ BW VNNI
Ice Lake            : CD VL DQ BW IFMA VBMI VBMI2 VPOPCNTDQ BITALG VNNI VPCLMULQDQ GFNI VAES
Tiger Lake          : CD VL DQ BW IFMA VBMI VBMI2 VPOPCNTDQ BITALG VNNI VPCLMULQDQ GFNI VAES VP2INTERSECT

GFNI (Galois Field Affine Transformation), VPCLMULQDQ, and VAES are not AVX-512 features per se.
Together with AVX-512, they enable EVEX encoded versions of GFNI, PCLMULQDQ, and AES instructions.

Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------

RDRAND              : Returning random numbers from an on-chip hardware random number generator.
RDSEED              : Loads a hardware generated random value and store it in the destination register.
AESNI               : Advanced Encryption Standard Instruction Set
VMX                 : Virtual Machine Extensions
FPU                 : Floating Point Unit on chip
VME                 : Virtual 8086 Mode Enhancements
DE                  : Debugging Extensions. Support for I/O breakpoints.
PSE                 : Page Size Extension
TSC                 : Time Stamp Counter. The RDTSC instruction is supported.
MSR                 : Model Specific Registers RDMSR and WRMSR Instructions.
PAE                 : Physical Address Extension
CX8                 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is supported.
APIC                : Processor contains an Advanced Programmable Interrupt Controller (APIC) on board.

Test results on as many different machines as possible are very welcome. Thank you.

Gunther

Hi Gunther,

AVX-512 is not detected on the new version 

Code Select Expand

CPU strings:
------------

Processor Vendor String: GenuineIntel
Processor Brand String:  11thGenIntel(R)Core(TM)i7-11800H@2.30GHz

Features by Processor and Operating System:
-------------------------------------------

Supported Instruction Sets: MMX  SSE  SSE2  SSE3  SSSE3  SSE4.1  SSE4.2  AVX  AVX2

Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------

RDRAND              : Returning random numbers from an on-chip hardware random number generator.
RDSEED              : Loads a hardware generated random value and store it in the destination register.
AESNI               : Advanced Encryption Standard Instruction Set
VMX                 : Virtual Machine Extensions
FPU                 : Floating Point Unit on chip
VME                 : Virtual 8086 Mode Enhancements
DE                  : Debugging Extensions. Support for I/O breakpoints.
PSE                 : Page Size Extension
TSC                 : Time Stamp Counter. The RDTSC instruction is supported.
MSR                 : Model Specific Registers RDMSR and WRMSR Instructions.
PAE                 : Physical Address Extension
CX8                 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is supported.
APIC                : Processor contains an Advanced Programmable Interrupt Controller (APIC) on board.

Press any key to continue...

[Gunther]

AVX-512 is not detected on the new version 

I see. But it works fine with my Skylake.

Code Select Expand


CPU strings:
------------

Processor Vendor String: GenuineIntel
Processor Brand String:  Intel(R)Core(TM)i7-7820XCPU@3.60GHz

Features by Processor and Operating System:
-------------------------------------------

Supported Instruction Sets: MMX  SSE  SSE2  SSE3  SSSE3  SSE4.1  SSE4.2  AVX  AVX2  AVX-512 F

It's safe to use the following AVX-512 extensions with this machine:
--------------------------------------------------------------------

AVX-512 DQ          : Vector Double Word and Quad Word
AVX-512 CD          : Efficient conflict detection to allow more loops to be vectorized.
AVX-512 BW          : Extends AVX-512 to cover 8-bit and 16-bit integer operations.
AVX-512 VL          : Extends most AVX-512 operations to also operate on XMM and YMM registers.[


Do you have any guesses as to where the problem lies? The Iset procedure works exactly according to Intel's recommendations. Nevertheless, I will analyze this again in the next few days.
Have you tested the old version as well?

[LiaoMi]

Hi Gunther,

AVX-512 is not detected on the new version 

I see. But it works fine with my Skylake.

Code Select Expand


CPU strings:
------------

Processor Vendor String: GenuineIntel
Processor Brand String:  Intel(R)Core(TM)i7-7820XCPU@3.60GHz

Features by Processor and Operating System:
-------------------------------------------

Supported Instruction Sets: MMX  SSE  SSE2  SSE3  SSSE3  SSE4.1  SSE4.2  AVX  AVX2  AVX-512 F

It's safe to use the following AVX-512 extensions with this machine:
--------------------------------------------------------------------

AVX-512 DQ          : Vector Double Word and Quad Word
AVX-512 CD          : Efficient conflict detection to allow more loops to be vectorized.
AVX-512 BW          : Extends AVX-512 to cover 8-bit and 16-bit integer operations.
AVX-512 VL          : Extends most AVX-512 operations to also operate on XMM and YMM registers.[


Do you have any guesses as to where the problem lies? The Iset procedure works exactly according to Intel's recommendations. Nevertheless, I will analyze this again in the next few days.
Have you tested the old version as well?

on the last check, the transition to AVX-512 does not work, I have rax = 0Dh

Code Select Expand

.text:00000001400011A6 loc_1400011A6:
.text:00000001400011A6 cmp     rax, 0Dh
.text:00000001400011AA jnz     short loc_1400011C1

then there is a jump to this code 

Code Select Expand

.text:00000001400011AC lea     rcx, Format
.text:00000001400011B3 lea     rdx, aMmxSseSse2Sse3_4 ;
.text:00000001400011BA call    sub_140001C95
.text:00000001400011BF jmp     short loc_1400011DA

The old version produces the same result 

[zedd151]

From my (estimated) 10+ year old box...

Code Select Expand


CPU strings:
------------


Processor Vendor String: GenuineIntel
Processor Brand String:  Intel(R)Core(TM)2DuoCPUE8400@3.00GHz


Features by Processor and Operating System:
-------------------------------------------


Supported Instruction Sets: MMX  SSE  SSE2  SSE3  SSSE3  SSE4.1


Your CPU supports the following additional instructions and features:
---------------------------------------------------------------------


VMX                 : Virtual Machine Extensions
SMX                 : Safer Mode Extensions
FPU                 : Floating Point Unit on chip
VME                 : Virtual 8086 Mode Enhancements
DE                  : Debugging Extensions. Support for I/O breakpoints.
PSE                 : Page Size Extension
TSC                 : Time Stamp Counter. The RDTSC instruction is supported.
MSR                 : Model Specific Registers RDMSR and WRMSR Instructions.
PAE                 : Physical Address Extension
CX8                 : CMPXCHG8B instruction (compare-and-exchange 8 bytes) is su
pported.
APIC                : Processor contains an Advanced Programmable Interrupt Cont
roller (APIC) on board.


Press any key to continue...

[Gunther]

From my (estimated) 10+ year old box...

Thanks for your test.  However, the problem is with the AVX-512 detection.

[zedd151]

Thanks for your test.  However, the problem is with the AVX-512 detection.

Test was a success then. Now I know I don't have it.   

[HSE]

Hi Gunther!

I added check of bit 12 for FMA to obtain:

Code Select Expand

Supported Instruction Sets: MMX  SSE  SSE2  SSE3  SSSE3  SSE4.1  SSE4.2  AVX  AVX2  FMA

I don't know if that way is correct.

Thanks, HSE

[Gunther]

HSE,

I don't know if that way is correct.

I don't know at the moment either. But as well as I find time next week, I will have a look. But already now a thank you to you. 

[HSE]