Instruction Set detection for (?)

[FORTRANS]

Hi,
   
   See the thread "Instruction Set detection for 32 bit Operating
Systems" for the background of running CPUID programs on older
computers.  Moderator, if you feel this should be a part of that,
merge the threads.  Or move to a better subforum if appropriate.

   I have an old CPU information program from Intel that runs under
windows.  Two versions, 16-bit and 32-bit that even mentions Win32s
(though it still won't work with it).  The 16-bit works as a window,
and displays minimal information.  It shows "CPUINFO16 DLL Version:
1.1".  It was from the 1996 time frame.

   So I looked for a more current version, and based on a link posted
on the forum I found one.  I used a text extract tool to get the
CPUID3A.ASM and CPUID3B.ASM programs from; Order Number:
241618-038, "Intel (R) Processor Identification and the CPUID
Instruction", Application Note 485, April 2012.  I did some minimal
clean up to compensate for the lines wrapping in places.  There do
seem to be some remaining errors.  The garbage following "This
processor: GenuineIntel" should not occur with the P-III for
instance (AFAICT).

   Off and on, I am editing the files to restore the formatting lost
in the extraction.  Maybe a quarter of the way through that.  If I
can figure out how to fix an error I will do that.

   I assembled and linked the program as a DOS program.  If someone
took the related C program, it can apparently be made into a protected
mode program.

Regards

Steve N.

Code Select Expand

{Program output P-III.}

CPUID data documented in the Intel(R) 64 and IA-32 Software Developer Manual
Volume 2A Instruction Set A-L, March 2012 [doc #253666]
http://www.intel.com/products/processor/manuals/index.htm

This processor: GenuineIntel vFân+ 



   GenuineIntelGenuineIntelâ          ·â                                                               

                                                               

        é                                                                 This processor:
Processor Signature: 00000683h
Family Data: 006h
Model Data : 08h
Stepping : 3h

Maximum CPUID Standard and Extended Functions:
CPUID.(EAX=00h):EAX: 02h
CPUID.(EAX=80000000h):EAX: 03020101h

CPUID.(EAX=01h):ECX Supported Features: 00000000h
CPUID.(EAX=01h):EDX Supported Features: 0383F9FFh
  FPU VME DE PSE TSC MSR PAE MCE CX8 SEP MTRR PGE MCA CMOV PAT PSE36 MMX FXSR SSE

CPUID.(EAX=01h) Leaf:
Brand Index : 2
CLFLUSH Line Size: 0 bytes
Max Addressable IDs for logical processors in physical package:0
Initial APIC ID : 00h

{Program output Pentium.}

CPUID data documented in the Intel(R) 64 and IA-32 Software Developer Manual
Volume 2A Instruction Set A-L, March 2012 [doc #253666]
http://www.intel.com/products/processor/manuals/index.htm

This processor: GenuineIntel Pentium(R)
Processor Signature: 00000570h
Family Data: 005h
Model Data : 07h
Stepping : 0h

Maximum CPUID Standard and Extended Functions:
CPUID.(EAX=00h):EAX: 01h
CPUID.(EAX=80000000h):EAX: 00000000h

CPUID.(EAX=01h):ECX Supported Features: 00000000h
CPUID.(EAX=01h):EDX Supported Features: 000001BFh
  FPU VME DE PSE TSC MSR MCE CX8

CPUID.(EAX=01h) Leaf:
Brand Index : 0
CLFLUSH Line Size: 0 bytes
Max Addressable IDs for logical processors in physical package:0
Initial APIC ID : 00h

{Program output Pentium(R) M.}

CPUID data documented in the Intel(R) 64 and IA-32 Software Developer Manual
Volume 2A Instruction Set A-L, March 2012 [doc #253666]
http://www.intel.com/products/processor/manuals/index.htm

This processor: GenuineIntel
Brand String: Intel(R) Pentium(R) M processor 1.70GHz
Processor Signature: 000006D6h
Family Data: 006h
Model Data : 0Dh
Stepping : 6h

Maximum CPUID Standard and Extended Functions:
CPUID.(EAX=00h):EAX: 02h
CPUID.(EAX=80000000h):EAX: 80000004h

CPUID.(EAX=01h):ECX Supported Features: 00000180h
  EIST TM2
CPUID.(EAX=01h):EDX Supported Features: AFE9F9BFh
  FPU VME DE PSE TSC MSR MCE CX8 SEP MTRR PGE MCA CMOV PAT CLFSH DS ACPI MMX FXSR SSE SSE2 SS TM PBE
CPUID.(EAX=80000001h):ECX Supported Features: 00000000h
CPUID.(EAX=80000001h):EDX Supported Features: 00000000h

CPUID.(EAX=01h) Leaf:
Brand Index : 22
CLFLUSH Line Size: 64 bytes
Max Addressable IDs for logical processors in physical package:0
Initial APIC ID : 00h

[Gunther]

Steve,

I think it's the program which Intel provides inside the example section of the "Intel Processor Identification and the CPUID instruction" manual (application note 485) from May 2012. It has a hole bunch of information (see below). The point is, it doesn't check the OS support for SSE and AVX. But it can serve as a blueprint for a good diagnostic tool.

Code Select Expand


CPUID data documented in the Intel(R) 64 and IA-32 Software Developer Manual
Volume 2A Instruction Set A-L, March 2012 [doc #253666]
http://www.intel.com/products/processor/manuals/index.htm

This processor: GenuineIntel
Brand String: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz
Processor Signature: 000306A9h
Family Data: 006h
Model Data : 3Ah
Stepping : 9h

Maximum CPUID Standard and Extended Functions:
CPUID.(EAX=00h):EAX: 0Dh
CPUID.(EAX=80000000h):EAX: 80000008h

CPUID.(EAX=01h):ECX Supported Features: 77BAE3FFh
  SSE3 PCLMULQDQ DTES64 MONITOR DS-CPL VMX SMX EIST TM2 SSSE3 CMPXCHG16B XTPR PD
CM PCID SSE4.1 SSE4.2 x2APIC POPCNT TSC-DEADLINE AES XSAVE AVX F16C RDRAND
CPUID.(EAX=01h):EDX Supported Features: BFEBFBFFh
  FPU VME DE PSE TSC MSR PAE MCE CX8 APIC SEP MTRR PGE MCA CMOV PAT PSE36 CLFSH
DS ACPI MMX FXSR SSE SSE2 SS HTT TM PBE
CPUID.(EAX=06h):EAX Supported Features: 00000077h
  DIGTEMP TRBOBST ARAT PLN ECMD PTM
CPUID.(EAX=06h):ECX Supported Features: 00000009h
  MPERF-APERF-MSR ENERGY-EFF
CPUID.(EAX=80000001h):ECX Supported Features: 00000001h
  LAHF-SAHF
CPUID.(EAX=80000001h):EDX Supported Features: 28100000h
  XD RDTSCP EM64T
CPUID.(EAX=80000007h):EDX Supported Features: 00000100h
  INVTSC

CPUID.(EAX=01h) Leaf:
Brand Index : 0
CLFLUSH Line Size: 64 bytes
Max Addressable IDs for logical processors in physical package:16
Initial APIC ID : 02h

CPUID.(EAX=04h) Deterministic Cache Parameters (DCP) Leaf n=0:
  Data  Cache; Level 1; Size 32 KB
    Self Initializing
    Max # of addressable IDs for logical processors sharing this cache: 2
    Max # of addressable IDs for processor cores in physical package : 8
    WBINVD/INVD is not guaranteed to act upon lower level threads of non-origina
ting threads sharing this cache
    Cache is not inclusive of lower cache levels
    Direct mapped cache
CPUID.(EAX=04h) Deterministic Cache Parameters (DCP) Leaf n=1:
  Instruction Cache; Level 1; Size 32 KB
    Self Initializing
    Max # of addressable IDs for logical processors sharing this cache: 2
    Max # of addressable IDs for processor cores in physical package : 8
    WBINVD/INVD is not guaranteed to act upon lower level threads of non-origina
ting threads sharing this cache
    Cache is not inclusive of lower cache levels
    Direct mapped cache
CPUID.(EAX=04h) Deterministic Cache Parameters (DCP) Leaf n=2:
  Unified  Cache; Level 2; Size 256 KB
    Self Initializing
    Max # of addressable IDs for logical processors sharing this cache: 2
    Max # of addressable IDs for processor cores in physical package : 8
    WBINVD/INVD is not guaranteed to act upon lower level threads of non-origina
ting threads sharing this cache
    Cache is not inclusive of lower cache levels
    Direct mapped cache
CPUID.(EAX=04h) Deterministic Cache Parameters (DCP) Leaf n=3:
  Unified  Cache; Level 3; Size 8192 KB
    Self Initializing
    Max # of addressable IDs for logical processors sharing this cache: 16
    Max # of addressable IDs for processor cores in physical package : 8
    WBINVD/INVD is not guaranteed to act upon lower level threads of non-origina
ting threads sharing this cache
    Cache is inclusive of lower cache levels
    Complex function is used to index the cache

CPUID.(EAX=05h) Monitor/MWAIT Leaf:
Smallest monitor line size: 64 bytes
Largest monitor line size: 64 bytes
Enumeration of Monitor-MWAIT extensions: Supported
Interrupts as break-event for MWAIT: Supported
Number of C0 sub C-states supported using MWAIT: 0
Number of C1 sub C-states supported using MWAIT: 2; C1E Supported
Number of C2 sub C-states supported using MWAIT: 1
Number of C3 sub C-states supported using MWAIT: 1
Number of C4 sub C-states supported using MWAIT: 0

CPUID.(EAX=06h) Thermal and Power Management Leaf:
Number of Interrupt Thresholds: 2

CPUID.(EAX=09h) Direct Cache Access Leaf:
Value of MSR PLATFORM_DCA_CAP[31:0]: 00000000h

CPUID.(EAX=0Ah) Architecture Performance Monitoring Leaf:
Version ID: 3
Number of General Purpose Counters per Logical Processor: 4
Bit Width of General Purpose Counters: 48
Length of EBX bit vector to enumerate events: 7
Core Cycle event : Available
Instruction Retired event : Available
Reference Cycles event : Available
Last-Level Cache Reference event: Available
Last-Level Cache Misses event : Available
Branch Instruction Retired event: Available
Branch Mispredict Retired event : Available
Number of Fixed-Function Performance Counters: 3
Bit Width of Fixed-Function Performance Counters: 48

CPUID.(EAX=0Bh) Extended Topology Leaf n=0:
  x2APIC ID bits to shift right to get unique topology ID: 1
  Logical processors at this level type: 2
  Level Number: 0 (Thread)
  Level Type : 1 (SMT)
  x2APIC ID : 2
CPUID.(EAX=0Bh) Extended Topology Leaf n=1:
  x2APIC ID bits to shift right to get unique topology ID: 4
  Logical processors at this level type: 8
  Level Number: 1 (Core)
  Level Type : 2 (Core)
  x2APIC ID : 2

CPUID.(EAX=0Dh) Processor Extended State Enumeration Main Leaf n=0:
  Valid bit fields of XCR0[31: 0]: 00000000000000000000000000000111b
  Valid bit fields of XCR0[63:32]: 00000000000000000000000000000000b
  Max size required by enabled features in XCR0: 832 bytes
  Max size required by XSAVE/XRSTOR for supported features: 832 bytes
CPUID.(EAX=0Dh) Processor Extended State Enumeration Sub-Leaf n=1:
XSAVEOPT instruction: Supported
CPUID.(EAX=0Dh) Processor Extended State Enumeration Sub-Leaf n=2:
Size required for feature associated with sub-leaf: 256 bytes
Offset of save area from start of XSAVE/XRSTOR area: 576

CPUID.(EAX=80000006h) Extended L2 Cache Features:
L2 Cache Size: 256 KB
L2 Cache Associativity: 8-way
L2 Cache Line Size: 64 bytes

CPUID.(EAX=80000008h) Physical and Virtual Address Sizes:
Physical Address bits: 36
Virtual Address bits : 48


Gunther

[dedndave]

Prescott w/HTT

Code Select Expand

This processor: GenuineIntel
Brand String: Intel(R) Pentium(R) 4 CPU 3.00GHz
Processor Signature: 00000F43h
Family Data: 00Fh
Model Data : 04h
Stepping : 3h

Maximum CPUID Standard and Extended Functions:
CPUID.(EAX=00h):EAX: 05h
CPUID.(EAX=80000000h):EAX: 80000008h

CPUID.(EAX=01h):ECX Supported Features: 0000649Dh
  SSE3 DTES64 MONITOR DS-CPL EIST CNXT-ID CMPXCHG16B XTPR
CPUID.(EAX=01h):EDX Supported Features: BFEBFBFFh
  FPU VME DE PSE TSC MSR PAE MCE CX8 APIC SEP MTRR PGE MCA CMOV PAT PSE36 CLFSH DS ACPI MMX FXSR SSE SSE2 SS HTT TM PBE
CPUID.(EAX=80000001h):ECX Supported Features: 00000000h
CPUID.(EAX=80000001h):EDX Supported Features: 20100000h
  XD EM64T
CPUID.(EAX=80000007h):EDX Supported Features: 00000000h

CPUID.(EAX=01h) Leaf:
Brand Index : 0
CLFLUSH Line Size: 64 bytes
Max Addressable IDs for logical processors in physical package:2
Initial APIC ID : 01h

CPUID.(EAX=04h) Deterministic Cache Parameters (DCP) Leaf n=0:
  Data  Cache; Level 1; Size 16 KB
    Self Initializing
    Max # of addressable IDs for logical processors sharing this cache: 2
    Max # of addressable IDs for processor cores in physical package : 1
    WBINVD/INVD is not guaranteed to act upon lower level threads of non-originating threads sharing this cache
    Cache is not inclusive of lower cache levels
    Direct mapped cache
CPUID.(EAX=04h) Deterministic Cache Parameters (DCP) Leaf n=1:
  Unified  Cache; Level 2; Size 2048 KB
    Self Initializing
    Max # of addressable IDs for logical processors sharing this cache: 2
    Max # of addressable IDs for processor cores in physical package : 1
    WBINVD/INVD is not guaranteed to act upon lower level threads of non-originating threads sharing this cache
    Cache is not inclusive of lower cache levels
    Direct mapped cache

CPUID.(EAX=05h) Monitor/MWAIT Leaf:
Smallest monitor line size: 64 bytes
Largest monitor line size: 64 bytes
Enumeration of Monitor-MWAIT extensions: Unsupported
Interrupts as break-event for MWAIT: Unsupported
Number of C0 sub C-states supported using MWAIT: 0
Number of C1 sub C-states supported using MWAIT: 0
Number of C2 sub C-states supported using MWAIT: 0
Number of C3 sub C-states supported using MWAIT: 0
Number of C4 sub C-states supported using MWAIT: 0

CPUID.(EAX=80000006h) Extended L2 Cache Features:
L2 Cache Size: 2048 KB
L2 Cache Associativity: 8-way
L2 Cache Line Size: 64 bytes

CPUID.(EAX=80000008h) Physical and Virtual Address Sizes:
Physical Address bits: 36
Virtual Address bits : 48

[FORTRANS]

Hi,

   I booted up my oldest Pentium computer today in a futile
attempt to recover some files.  But I did run the CPUID3A
program, and its output differed from the Pentium that I
reported upon above.  So here it is.

Code Select Expand

CPUID data documented in the Intel(R) 64 and IA-32 Software Developer Manual
Volume 2A Instruction Set A-L, March 2012 [doc #253666]
http://www.intel.com/products/processor/manuals/index.htm

This processor: GenuineIntel Pentium(R)
Processor Signature: 00000521h
Family Data: 005h
Model Data : 02h
Stepping : 1h

Maximum CPUID Standard and Extended Functions:
CPUID.(EAX=00h):EAX: 01h
CPUID.(EAX=80000000h):EAX: 00000000h

CPUID.(EAX=01h):ECX Supported Features: 00000000h
CPUID.(EAX=01h):EDX Supported Features: 000001BFh
  FPU VME DE PSE TSC MSR MCE CX8

CPUID.(EAX=01h) Leaf:
Brand Index : 0
CLFLUSH Line Size: 0 bytes
Max Addressable IDs for logical processors in physical package:0
Initial APIC ID : 00h

   I also tested another Pentium, that I thought was the same as
the first one, but it was different as well.

Code Select Expand

CPUID data documented in the Intel(R) 64 and IA-32 Software Developer Manual
Volume 2A Instruction Set A-L, March 2012 [doc #253666]
http://www.intel.com/products/processor/manuals/index.htm

This processor: GenuineIntel Pentium(R)
Processor Signature: 0000052Ch
Family Data: 005h
Model Data : 02h
Stepping : Ch

Maximum CPUID Standard and Extended Functions:
CPUID.(EAX=00h):EAX: 01h
CPUID.(EAX=80000000h):EAX: 00000000h

CPUID.(EAX=01h):ECX Supported Features: 00000000h
CPUID.(EAX=01h):EDX Supported Features: 000001BFh
  FPU VME DE PSE TSC MSR MCE CX8

CPUID.(EAX=01h) Leaf:
Brand Index : 0
CLFLUSH Line Size: 0 bytes
Max Addressable IDs for logical processors in physical package:0
Initial APIC ID : 00h

Regards,

Steve N.

[Gunther]

Steve,

Intel has a long list in the CPUID and processor detection manual for model, stepping etc.

Gunther 

[dedndave]

that's an older version, Gunther
the latest is -036 i think

then, for specific processors...

ftp://download.intel.com/support/processors/

ftp://download.intel.com/support/processors/pentiumiii/sb/24445355.pdf

this makes it a little easier

http://ark.intel.com/

[FORTRANS]

that's an older version, Gunther
the latest is -036 i think

Hi,

   See above in the initial post, I was using -38.

then, for specific processors...

ftp://download.intel.com/support/processors/

ftp://download.intel.com/support/processors/pentiumiii/sb/24445355.pdf

this makes it a little easier

http://ark.intel.com/

   Thanks for the links.  Interesting.

Regards,

Steve N.

[Gunther]

Dave,

thank you for the interesting links.  :t

Gunther

[dedndave]

it would seem that intel is no longer publishing that document
at least - i am not able to locate it on their site
all their CPUID links point to the software developers manuals
it is 241618 aka AP-485

i was able to find version 039, however - and it seems to be a substantial update

https://www.scss.tcd.ie/Jeremy.Jones/CS4021/processor-identification-cpuid-instruction-note.pdf

[Gunther]

Dave,

i was able to find version 039, however - and it seems to be a substantial update
https://www.scss.tcd.ie/Jeremy.Jones/CS4021/processor-identification-cpuid-instruction-note.pdf

yes, it is.  :t

Gunther

[FORTRANS]

Hi,

it would seem that intel is no longer publishing that document
at least - i am not able to locate it on their site
all their CPUID links point to the software developers manuals
it is 241618 aka AP-485

   Yeah, all their links seem broken.

i was able to find version 039, however - and it seems to be a substantial update

   Thanks.  Yeah, -38 was quite a bit different than -36.  I got
the -38 version from a link on the forum, but I can't find it now.

   One interesting item was the following.

Application Note 39
Output of the CPUID Instruction
5.1.8 Structured Extended Feature Flags Enumeration (Function 07h)
When EAX is initialized to a value of 7, the CPUID instruction returns
structured extended features flags in the EBX register. This function
requires ECX to be initialized with a sub-leaf number. When the function
is executed with ECX = 0, EAX will contain the maximum supported sub-leaf.
When this function is executed with ECX = 0 (sub-leaf 0), a return
value of EAX=EBX=ECX=EDX=0 indicates no sub leaves are supported.

Table 5-12. Structured Extended Feature Flags Parameters
Register Bits Description
EAX[31:0] Reports the maximum supported leaf 7 sub-leaf.
EBX[31:11] Reserved
EBX[10] INVPCID. If 1, supports INVPCID instruction for system software
        that manages process-context identifiers.
EBX[9] Supports Enhanced REP MOVSB/STOSB if 1.
EBX[8] Reserved
EBX[7] SMEP. Supports Supervisor Mode Execution Protection if 1.
EBX[6:1] Reserved
EBX[0] FSGSBASE. Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.
ECX[31:0] Reserved
EDX[31:0] Reserved

   In one of their optimization documents, they have test results for
the Enhanced REP MOVSB/STOSB.  Looks like it would be worth
investigating.

Regards,

Steve N.

[Gunther]

   In one of their optimization documents, they have test results for
the Enhanced REP MOVSB/STOSB.  Looks like it would be worth
investigating.

No doubt about that.

Gunther