Author Topic: My version of a CPU identification utility  (Read 23478 times)

dedndave

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Re: My version of a CPU identification utility
« Reply #15 on: February 22, 2014, 06:31:39 AM »
that one works, Timppa   :t

results for prescott w/htt...
Code: [Select]
Extended + family ID: 0f
Extended + model ID: 04
Stepping: 3
Unknown microarchitecture
CPU has FP unit.
CPU has MMX.
CPU has SSE.
CPU has SSE2.
CPU has SSE3.
CPU does not have SSE 4.1.
CPU does not have SSE 4.2.
CPU does not have AVX.
not sure about the "microarchitecture" value - but the rest appears to be correct

Gunther

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Re: My version of a CPU identification utility
« Reply #16 on: February 22, 2014, 10:49:05 AM »
Mark,

Back about 20 years ago I was a co-author of a book on targeting DOS using assembly, and did a lot of work with Borland's Turbo Assembler (TASM). I did all of the compiling/assembling and linking from the command line. At the moment I'm doing everything through VS, and the switches for MASM (via VS) are something of a mystery to me, although I'm coming along.
there are a few old TASM fans floating around here (including me). But unfortunately, it's no longer maintained.

A real assembly language coder should be capable to do the necessary steps via the command line. I'm sure you can do it, too.
jwasm -h brings for example:
Code: [Select]
JWasm v2.08a, Sep  7 2012, Masm-compatible assembler.
Portions Copyright (c) 1992-2002 Sybase, Inc. All Rights Reserved.
Source code is available under the Sybase Open Watcom Public License.

   JWasm [options] asm-file [options] [asm-file] ... [@env_var]

 options:
-<0|1|..|10>[p]      Set CPU: 0=8086 (default), 1=80186, 2=80286, 3=80386,
                     4=80486, 5=Pentium, 6=PPro, 7=P2, 8=P3, 9=P4, 10=x86-64.
                     <p> allows privileged instructions.
-c                   Assemble without linking (always set)
-C<p|u|x>            Set OPTION CASEMAP: p=NONE, u=ALL,
                     x=NOTPUBLIC (default).
-D<name>[=text]      Define text macro
-e<number>           Set error limit number (default=50)
-EP                  Output preprocessed listing to stdout
-eq                  don't display error messages
-Fd[=<file_name>]    Write import definition file
-Fi<file_name>       Force <file_name> to be included
-Fl[=<file_name>]    Write listing file
-Fo<file_name>       Set object file name
-Fw<file_name>       Set errors file name
-FPi                 80x87 instructions with emulation fixups
-FPi87               80x87 instructions (default)
-fpc                 Disallow floating-point instructions (.NO87)
-fp<n>               Set FPU, <n> is: 0=8087 (default), 2=80287, 3=80387
-G<c|d|z>            Use Pascal, C or Stdcall calling convention
-I<directory>        Add directory to list of include directories
-m<t|s|c|m|l|h|f>    Set memory model:
                     (Tiny, Small, Compact, Medium, Large, Huge, Flat)
-nc=<name>           Set class name of code segment
-n<d|m|t>=<name>     Set name of data segment, module or text segment
-q, -nologo          Don't display version and copyright information
-Sa                  Maximize source listing
-safeseh             Assert all exception handlers are declared
-Sf                  Generate first pass listing
-Sg                  Display generated code in listing
-Sn                  Suppress symbol-table listing
-Sx                  List false conditionals
-w                   Same as /W0 /WX
-W<number>           Set warning level number (default=2, max=4)
-WX                  Treat all warnings as errors
-X                   Ignore INCLUDE environment path
-zcm                 C names are decorated with '_' prefix (default)
-zcw                 No name decoration for C symbols
-Zd                  Add line number debug info (OMF & COFF only)
-Zf                  Make all symbols public
-zf<0|1>             Set FASTCALL type: 0=MS VC style (default),
                     1=OW register calling convention
-Zg                  Generated code is to exactly match Masm's one
-Zi                  Add symbolic debug info (OMF & COFF only)
-zlc                 No OMF records about data in code
-zld                 No OMF records about far call optimization
-zlf                 No COFF .file entry in symbol table
-zls                 No COFF auxiliary entries for sections in symbol table
-Zm                  Masm v5.1 compatibility
-Zne                 Disable syntax extensions not supported by Masm
-Zp[n]               Set structure alignment, n=<1|2|4|8|16|32>
-Zs                  Perform syntax check only
-zt<0|1|2>           Set STDCALL symbol decoration: 0=No name decoration,
                     1=No '@size' suffix for functions, 2=Full (default)
-Zv8                 Enable Masm v8+ PROC visibility
-zze                 No name decoration for exported symbols
-zzs                 Store decorated name of start address (COFF only)
@env_var             Environment variable or file containing further commands
output formats:
-bin                 plain binary file
-coff                32-bit COFF format object file
-elf                 32-bit ELF format object file
-elf64               64-bit ELF format object file
-mz                  DOS MZ binary file
-omf                 OMF format object file (default)
-win64               64-bit COFF format object file
and yasm -h brings:
Code: [Select]
usage: yasm [option]* file
Options:
    --version               show version text
    --license               show license text
    -h, --help              show help text
    --arch=<arch>           select architecture (list with -a help)
     -a <arch>
    --parser=<parser>       select parser (list with -p help)
     -p <parser>
    --preproc=<preproc>     select preprocessor (list with -r help)
     -r <preproc>
    --oformat=<format>      select object format (list with -f help)
     -f <format>
    --dformat=<debug>       select debugging format (list with -g help)
     -g <debug>
    --lformat=<list>        select list format (list with -L help)
     -L <list>
    --list=<listfile>       name of list-file output
     -l <listfile>
    --objfile=<filename>    name of object-file output
     -o <filename>
    --mapfile=<filename>    name of map-file output
    --machine=<machine>     select machine (list with -m help)
     -m <machine>
    --force-strict          treat all sized operands as if `strict' was used
    -w                      inhibits warning messages
    -W                      enables/disables warning
    -M                      generate Makefile dependencies on stdout
    -E <file>               redirect error messages to file
    -s                      redirect error messages to stdout
    -e, --preproc-only      preprocess only (writes output to stdout by default)

    -i <path>               add include path
    -I <path>               add include path
    -P <filename>           pre-include file
    -d <macro[=value]>      pre-define a macro, optionally to value
    -D <macro[=value]>      pre-define a macro, optionally to value
    -u <macro>              undefine a macro
    -U <macro>              undefine a macro
    -X <style>              select error/warning message style (`gnu' or `vc')
    --prefix=<prefix>       prepend argument to name of all external symbols
    --suffix=<suffix>       append argument to name of all external symbols
    --postfix=<suffix>      append argument to name of all external symbols

Files are asm sources to be assembled.

Sample invocation:
   yasm -f elf -o object.o source.asm

Report bugs to bug-yasm@tortall.net
It's easy to handle, just like in the good old DOS days.

Gunther
Get your facts first, and then you can distort them.

TWell

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Re: My version of a CPU identification utility
« Reply #17 on: February 22, 2014, 08:29:50 PM »
This version compiled with gcc.
asm part stripped to different file.

Gunther

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Re: My version of a CPU identification utility
« Reply #18 on: February 22, 2014, 10:15:03 PM »
Hi TWell,

your new version works like a charme. Interesting enough, you've done the external assembler part with GAS.  :t Is that your favorite tool? It performs not bad and one has the the feeling like in the good old days.

Gunther
Get your facts first, and then you can distort them.

TWell

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Re: My version of a CPU identification utility
« Reply #19 on: February 22, 2014, 11:06:41 PM »
Hi TWell,

your new version works like a charme. Interesting enough, you've done the external assembler part with GAS.  :t Is that your favorite tool? It performs not bad and one has the the feeling like in the good old days.

Gunther
(g)as is not my favorite at all.
I just made masm code first and then convert that object file for as.exe with ObjConv.exe and edit that file.

Gunther

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Re: My version of a CPU identification utility
« Reply #20 on: February 23, 2014, 12:02:21 AM »
TWell,

(g)as is not my favorite at all.
I just made masm code first and then convert that object file for as.exe with ObjConv.exe and edit that file.

okay. But you can link the masm code directly. Why that indirection?

Gunther
Get your facts first, and then you can distort them.

TWell

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Re: My version of a CPU identification utility
« Reply #21 on: February 23, 2014, 12:33:16 AM »
But you can link the masm code directly. Why that indirection?

Gunther
making that program just with gcc/as only.

EDIT: compiled with gcc 2.95.3 too
« Last Edit: February 23, 2014, 02:32:17 AM by TWell »

FORTRANS

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Re: My version of a CPU identification utility
« Reply #22 on: February 23, 2014, 12:46:47 AM »
Hi,

   I ran the program on an older machine, and the first version
did not run; "not a valid Win32 application"  The gcc version works.
Here is the output.

G:\WORK\CPUID>cpuinfo1
Extended + family ID: 06
Extended + model ID: 08
Stepping: 3
Microarchiture: Unknown

CPU has FP unit.
CPU has MMX.
CPU has SSE.
CPU does not have SSE2.
CPU does not have SSE3.
CPU does not have SSE 4.1.
CPU does not have SSE 4.2.
CPU does not have AVX.


   I can run it on some other old computers if wanted.

Steve N.

Mark44

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Re: My version of a CPU identification utility
« Reply #23 on: February 23, 2014, 04:07:52 AM »
dedndave and FORTRANS,
To identify the microarchitecture I used the information listed in the Intel Optimization Reference Manual (July 2013), in appendix C (section 3.1). I added a comment in my code listing my source for this info. The table I drew from lists only recent Intel microarchitectures - Haswell, Ivy Bridge, Sandy Bridge, Westmere, Nehalem, Enhanced Intel Core, Intel Core. All of these have family IDs of 06h, so the family ID of your (dedndave's) machine is not listed. The family ID of FORTRANS's machine is 06h, but your model ID of 08h isn't listed in the table I drew from.

I have an older version of the Intel optimization docs from 2007 that contains information about the processors that were current at that time. For a family ID of 0Fh and model ID of 3, 4, or 6 (dedndave's machine), the microarchitecture is NetBurst. The machine that FORTRANS is using isn't listed in that older table. FORTRANS's machine is obviously pretty old, as it supports only MMX and nothing newer. If someone has saved a copy of the Intel Optimization reference that is older than Nov 2007, it might be listed there.

I'm happy to see there was so much interest in the code I wrote! I will update my microarchitecture identification logic and repost the revised version within a couple of days.
Mark 

MichaelW

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Re: My version of a CPU identification utility
« Reply #24 on: February 23, 2014, 04:15:17 AM »
Mark,

I compiled your source from the first post in this thread with the VC++ Toolkit 2003 compiler, no problems, but a warning with /W3:

CPUInfo.c(153) : warning C4244: '=' : conversion from 'long' to 'short', possible loss of data

Running the exe on my P3 I get:
Code: [Select]
Extended + family ID: 06
Extended + model ID: 07
Stepping: 3
Microarchiture: Unknown

CPU has FP unit.
CPU has MMX.
CPU has SSE.
CPU does not have SSE2.
CPU does not have SSE3.
CPU does not have SSE 4.1.
CPU does not have SSE 4.2.
CPU does not have AVX.

All correct AFAIK, but when I run it on my 3.06GHz P4 Northwood (the first P4 with HT) I get:
Code: [Select]
Extended + family ID: 0f
Extended + model ID: 02
Stepping: 9
Unknown microarchitecture
CPU has FP unit.
CPU has MMX.
CPU has SSE.
CPU has SSE2.
CPU has SSE3.
CPU does not have SSE 4.1.
CPU does not have SSE 4.2.
CPU does not have AVX.


AFAIK the SSE3 is not correct, and as a test, since I don’t have any MASM version that can assemble SSE3 instructions set up, I assembled and linked this source with as/ld (no as warnings or errors):
Code: [Select]
.intel_syntax noprefix
.section .text
    lddqu xmm0, X
    ret
.section .data
.balign 16
X:
.octa 0

And running the exe on both systems I get exception number c000001eh, which per ntstatus.h is STATUS_INVALID_LOCK_SEQUENCE. But I suspect that this is not conclusive proof, because I seem to recall something about the OS needing to enable instruction set extensions.
Well Microsoft, here’s another nice mess you’ve gotten us into.

dedndave

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Re: My version of a CPU identification utility
« Reply #25 on: February 23, 2014, 06:47:28 AM »
Mark,
some time back, i wrote a test program that you may find useful

in the process of writing the code, i corrected some errors that were in the Intel manuals
i also added the AMD processors (at that time) to create a single BMP file

http://dedndave.x10.mx/files/Signature.zip

the nice thing is, that we managed to collect a lot of data from forum members
so - it's not just the program that's useful, but all the replies from those who posted results
you can see what values are returned by a variety of processors...

http://www.masmforum.com/board/index.php?topic=13044.0

at the moment, it's been downloaded 286 times   :lol:

Mark44

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Re: My version of a CPU identification utility
« Reply #26 on: February 23, 2014, 09:04:54 AM »
Mark,

I compiled your source from the first post in this thread with the VC++ Toolkit 2003 compiler, no problems, but a warning with /W3:

CPUInfo.c(153) : warning C4244: '=' : conversion from 'long' to 'short', possible loss of data

Running the exe on my P3 I get:
Code: [Select]
Extended + family ID: 06
Extended + model ID: 07
Stepping: 3
Microarchiture: Unknown

CPU has FP unit.
CPU has MMX.
CPU has SSE.
CPU does not have SSE2.
CPU does not have SSE3.
CPU does not have SSE 4.1.
CPU does not have SSE 4.2.
CPU does not have AVX.

All correct AFAIK, but when I run it on my 3.06GHz P4 Northwood (the first P4 with HT) I get:
Code: [Select]
Extended + family ID: 0f
Extended + model ID: 02
Stepping: 9
Unknown microarchitecture
CPU has FP unit.
CPU has MMX.
CPU has SSE.
CPU has SSE2.
CPU has SSE3.
CPU does not have SSE 4.1.
CPU does not have SSE 4.2.
CPU does not have AVX.


AFAIK the SSE3 is not correct, and as a test, since I don’t have any MASM version that can assemble SSE3 instructions set up, I assembled and linked this source with as/ld (no as warnings or errors):
Code: [Select]
.intel_syntax noprefix
.section .text
    lddqu xmm0, X
    ret
.section .data
.balign 16
X:
.octa 0

And running the exe on both systems I get exception number c000001eh, which per ntstatus.h is STATUS_INVALID_LOCK_SEQUENCE. But I suspect that this is not conclusive proof, because I seem to recall something about the OS needing to enable instruction set extensions.
I think you might be right. I seem to recall something saying that even though a particular technology was supported in the CPU, it also had to be supported in the OS. It might have been in the Intel Optimization reference, although I've been looking at some stuff by Agner Fog and it might have been in there.

Mark44

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Re: My version of a CPU identification utility
« Reply #27 on: February 23, 2014, 09:06:20 AM »
Mark,
some time back, i wrote a test program that you may find useful

in the process of writing the code, i corrected some errors that were in the Intel manuals
i also added the AMD processors (at that time) to create a single BMP file

http://dedndave.x10.mx/files/Signature.zip

Thanks, dedndave. I have tucked this away for future reference.
Quote from: dedndave
the nice thing is, that we managed to collect a lot of data from forum members
so - it's not just the program that's useful, but all the replies from those who posted results
you can see what values are returned by a variety of processors...

http://www.masmforum.com/board/index.php?topic=13044.0

at the moment, it's been downloaded 286 times   :lol:

Gunther

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Re: My version of a CPU identification utility
« Reply #28 on: February 23, 2014, 11:00:57 AM »
Hi Dave,

at the moment, it's been downloaded 286 times   :lol:

that's no longer up-to-date.  :lol: :lol: :lol: Here is the output:
Code: [Select]
          EAX: 0
          ECX: 120
          EDX: 00403AB0h
       cbSize: 120
dwCoreAffMask: 00000000000000000000000000000001b
dwIdCpuStatus: 00000000h
    bVendorID: 1
      bFamily: 6
   bExtFamily: 0
       bModel: 10
    bExtModel: 3
        bType: 0
        bStep: 9
     bMmxBits: 00000001b
   w3DNowBits: 0000000000000000b
     wSseBits: 0000000000111111b
   dwMiscBits: 00000000000100001011101111111111b
      szBrand: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz
     szVendor: GenuineIntel
        szMmx: MMX
      sz3DNow:
        szSse: SSE4.2
Press any key to continue ...

Gunther
Get your facts first, and then you can distort them.

Mark44

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Re: My version of a CPU identification utility
« Reply #29 on: February 23, 2014, 06:08:55 PM »
Here is an updated version, addressing some of the problems noted in this thread.

I added the architectures listed in the 2007 Intel docs (optimization reference), and fixed a bug where I picked an incorrect bit when checking for CPU support for AVX. The new code also does the right thing in checking for AVX support, by looking for support from both the CPU and the OS.

For those of you who modified my code for gcc, this code still has inline assembly. Here are the things I changed.

Changes in printCpuidData function:
1. Added a variable called OSXSAVE.
2. Added a couple of cases for family ID 6.
3. Added logic for family ID 15.
4. Corrected the bit extracted to determine CPU support for AVX.
5. Added logic to extract the bit for OSXSAVE.
6. Revised the logic to determine OS and CPU support for AVX.

Added AVXSupportInOS function - mostly inline assembly that calls XGETBV with ECX = 0. If bits 1 and 2 of EAX are set, XMM state and YMM State are supported in the OS.