Author Topic: AES-NI (AES New Instructions)  (Read 3635 times)


  • Guest
AES-NI (AES New Instructions)
« on: September 05, 2018, 11:37:25 PM »
Since circa 2010, a few Intel and AMD CPUs are including AES-NI (AES New Instructions) which provide support for accelerated AES encryption and decryption.

They are:
AESENC. This instruction performs a single round of encryption. The instruction combines the four steps of the AES algorithm - ShiftRows, SubBytes, MixColumns & AddRoundKey into a single instruction.
AESENCLAST. Instruction for the last round of encryption. Combines the ShiftRows, SubBytes, & AddRoundKey steps into one instruction.
AESDEC. Instruction for a single round of decryption. This combines the four steps of AES - InvShiftRows, InvSubBytes, InvMixColumns, AddRoundKey into a single instruction
AESDECLAST. Performs last round of decryption. It combines InvShiftRows, InvSubBytes, AddRoundKey into one instruction.
AESKEYGENASSIST is used for generating the round keys used for encryption.
AESIMC is used for converting the encryption round keys to a form usable for decryption using the Equivalent Inverse Cipher.
PCLMULQDQ   Carryless multiply (CLMUL)

Since I could not find any previous MASM venture on this subject I took as model this article and produced an equivalente in MASM. Since the mentioned article provides a good deal of explanation I will not attempt to advance deeper.

The source code builds either with MASM or UASM without modification.

Code: [Select]


  • Member
  • *****
  • Posts: 2365
Re: AES-NI (AES New Instructions)
« Reply #1 on: September 06, 2018, 12:50:18 AM »
Nice  :t
Creative coders use backward thinking techniques as a strategy.


  • Member
  • *****
  • Posts: 1367
Re: AES-NI (AES New Instructions)
« Reply #2 on: September 06, 2018, 03:05:13 AM »
 :icon14: Cool, seems like my current cpu supports this instructions. I had the same output as you aw, thanks once again.  :icon14:


  • Guest
Re: AES-NI (AES New Instructions)
« Reply #3 on: September 06, 2018, 05:56:52 PM »
:icon14: Cool, seems like my current cpu supports this instructions.
Discounting some very low-end, almost all CPUs since 2010 support AES-NI, namely:
Westmere based processors, specifically:
Westmere-EP (Xeon 56xx) (a.k.a. Gulftown Xeon 5600-series DP server model) processors.
Clarkdale processors (except Core i3, Pentium and Celeron).
Arrandale processors (except Celeron, Pentium, Core i3, Core i5-4XXM).
Sandy Bridge processors:
Desktop: all except Pentium, Celeron, Core i3.
Mobile: all Core i7 and Core i5. Several vendors have shipped BIOS configurations with the extension disabled; a BIOS update is required to enable them.
Ivy Bridge processors.
All i5, i7, Xeon and i3-2115C only.
Haswell processors (all except i3-4000m, Pentium and Celeron).
Broadwell processors (all except Pentium and Celeron).
Silvermont/Airmont processors (all except Bay Trail-D and Bay Trail-M).
Goldmont processors.
Skylake processors.
Kaby Lake processors.
Coffee Lake processors.

Several AMD processors support AES instructions:
Jaguar-based processors and newer
Puma-based processors and newer
"Heavy Equipment" processors
Bulldozer-based processors
Piledriver-based processors
Steamroller-based processors
Excavator-based processors and newer
Zen based procesors.

source Wikipedia


  • Member
  • *****
  • Posts: 1104
Re: AES-NI (AES New Instructions)
« Reply #4 on: September 07, 2018, 06:24:12 AM »

   Intel Core i3 results.


Steve N.


  • Member
  • ****
  • Posts: 896
Re: AES-NI (AES New Instructions)
« Reply #5 on: September 08, 2018, 08:14:07 PM »
The Intel® AES New Instructions (AES-NI) Sample Library demonstrates how one might implement a high performance Advanced Encryption Standard (AES) block cipher using the new AES-NI instructions available in Intel® Core™ i5, Intel® Core™ i7, Intel® Xeon® 5600 series and newer processors. All code samples can be compiled and run as native 32-bit or 64-bit binaries for both Microsoft Windows* and Linux* operating systems. This package is divided into three parts; The Intel® AES sample library, an AES example implementation using the library, and an application that compares Dr. Brian Gladman’s AES performance with that of the AES-NI optimized library. (3.17 MB)

White Paper (Shay Gueron) - Intel Architecture Group, Israel Development Center - Intel® Advanced Encryption Standard (AES) Instructions Set - Rev 3.01 -

Intel(R) Multi-Buffer Crypto for IPSec - AES-NI (Assembler & C Source code) -

Code: [Select]
Intel Multi-Buffer Crypto for IPsec Library is highly-optimized
software implementations of the core cryptographic processing for IPsec,
which provides industry-leading performance on a range of Intel(R) Processors.

For information on how to build and use this library, see the
Intel White Paper:
"Fast Multi-buffer IPsec Implementations on Intel Architecture Processors".
Jim Guilford, Sean Gulley, et. al.

The easiest way to find it is to search the Internet for the title and
Intel White Paper.

Table 1. List of supported cipher algorithms and their implementations.
|               |              Implementation                |
| Encryption    +--------------------------------------------|
|               | x86_64 | SSE    | AVX    | AVX2   | AVX512 |
| AES128-GCM    | N      | Y  by8 | Y  by8 | Y  by8 | N      |
| AES192-GCM    | N      | Y  by8 | Y  by8 | Y  by8 | N      |
| AES256-GCM    | N      | Y  by8 | Y  by8 | Y  by8 | N      |
| AES128-CCM    | Y(1)   | Y  by4 | Y  by8 | N      | N      |
| AES128-CBC    | N      | Y(2)   | Y(4)   | N      | N      |
| AES192-CBC    | N      | Y(2)   | Y(4)   | N      | N      |
| AES256-CBC    | N      | Y(2)   | Y(4)   | N      | N      |
| AES128-CTR    | N      | Y  by4 | Y  by8 | N      | N      |
| AES192-CTR    | N      | Y  by4 | Y  by8 | N      | N      |
| AES256-CTR    | N      | Y  by4 | Y  by8 | N      | N      |
| NULL          | Y      | N      | N      | N      | N      |
| AES128-DOCSIS | N      | Y(3)   | Y(5)   | N      | N      |
| DES-DOCSIS    | Y      | N      | N      | N      | Y  x16 |
| 3DES          | Y      | N      | N      | N      | Y  x16 |
| DES           | Y      | N      | N      | N      | Y  x16 |

The Design of RijndaeL: AES - The Advanced Encryption Standard (Information Security and Cryptography) 2002nd Edition


  • Guest
Re: AES-NI (AES New Instructions)
« Reply #6 on: September 08, 2018, 10:48:11 PM »
Nice addition  :t