Instruction sets introduced with different processors.

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A more or less useful description of what hardware introduced which instruction sets. Data from Wikipedia.

SSE2, Willamette New Instructions (WNI), introduced with the Pentium 4, is a major enhancement to
SSE. SSE2 adds two major features: double-precision (64-bit) floating point for all SSE operations,
and MMX integer operations on 128-bit XMM registers. In the original SSE instruction set, conversion
to and from integers placed the integer data in the 64-bit MMX registers. SSE2 enables the programmer
to perform SIMD math on any data type (from 8-bit integer to 64-bit float) entirely with the XMM
vector-register file, without the need to use the legacy MMX or FPU registers. It offers an orthogonal
set of instructions for dealing with common data types.

SSE3, also called Prescott New Instructions (PNI), is an incremental upgrade to SSE2, adding a
handful of DSP-oriented mathematics instructions and some process (thread) management instructions.

SSSE3, Merom New Instructions (MNI), is an upgrade to SSE3, adding 16 new instructions which include
permuting the bytes in a word, multiplying 16-bit fixed-point numbers with correct rounding, and
within-word accumulate instructions. SSSE3 is often mistaken for SSE4 as this term was used during
the development of the Core microarchitecture.

SSE4, Penryn New Instructions (PNI), is another major enhancement, adding a dot product instruction,
additional integer instructions, a popcnt instruction, and more.

XOP, FMA4 and CVT16 are new iterations announced by AMD in August 2007[2][3] and revised in May 2009.[4]

AVX (Advanced Vector Extensions), Gesher New Instructions (GNI), is an advanced version of SSE
announced by Intel featuring a widened data path from 128 bits to 256 bits and 3-operand instructions
(up from 2). Intel released processors in early 2011 with AVX support.[5] AVX requires support from
the operating system.

AVX2, also known as Haswell New Instructions (HNI), is an expansion of the AVX instruction set.

AVX-512 (3.1 and 3.2) are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD
instructions for x86 instruction set architecture.