Author Topic: UASM - Mixing VEX and EVEX in same procedure  (Read 501 times)

Leaeaxedx

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UASM - Mixing VEX and EVEX in same procedure
« on: May 29, 2021, 09:06:59 PM »
What options must be set for UASM to allow mixing VEX and EVEX instructions? With OPTION: EVEX: 1 only AVX512 instructions set is allowed (??), while AVX

vpand   xmm0,xmm1,xmm2  is an error (but not AVX 512 vpandd/q   xmm0,xmm1,xmm2).

This produces unnecessary size overhed.

Any help appreciated.

johnsa

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Re: UASM - Mixing VEX and EVEX in same procedure
« Reply #1 on: June 01, 2021, 07:50:28 PM »
Hi,

I've emailed you directly as well, but just for reference here.. I believe the issue you had was that you wrote
VPAND xmm0,xmm1,xmm20
xmm20 would only be a valid register for EVEX/AVX512 and would then required VPANDD
I've tested this with 2.53 and it's working as expected.

I've also added KTEST{b/w/d/q} to 2.53 branch as you were using them. There are still a lot of newer avx512 instructions still to be added.
I really hate Intel and there haphazard abuse of the ISA.. constantly adding new instructions.. it's ridiculous, I hope AMD NEVER add AVX512.. (personal rant) :)