Simple pulse counter and emitter program

[dedndave]

you are talking about the delay between Q outputs
because it is a ripple-carry counter, that is a possibility
but, when you are decoding a single specific value on the output, it shouldn't be an issue

you'll just have to trust me - lol
i have used similar decoding dividers many, many times   

[qWord]

you'll just have to trust me

I do  :P

[Paulo]

How about a "gated" counter?
An extra chip but this way no chance of glitches.
(note that RC time delay not shown on reset going to counter).

[georg]

hello Paulo, the idea is good, but how the output pulse is generated?, with your circuit will be needed an additional input clock to lower the output of the gate.

[qWord]

hello Paulo, the idea is good, but how the output pulse is generated?, with your circuit will be needed an additional input clock to lower the output of the gate.

The latch triggers on falling edges. Therefore the reset is delayed by the duration of the input pulse (AFAICS).

[qWord]

OK, I see - the latch needs also a rest input. Otherwise the output will be reset for the falling edge of the next pulse.

[Paulo]

hello Paulo, the idea is good, but how the output pulse is generated?, with your circuit will be needed an additional input clock to lower the output of the gate.

Good point, I missed that.
I will redraw the circuit.

[dedndave]

yes - that's the issue - between synchronous and asynchronous counters

synchronous counters use the same clock input for all stages
transitions on all ouptuts are synchronized



asynchronous counters (including ripple-carry counters like the 4040)
use the output of a previous stage to clock the next successive stage



when the later method is used, there are small periods
when the overall output value may be invalid, as qWord suggested
there are sometimes "glitches" or small spikes that might occur in a decoder
and - it can be overcome by latching the outputs, as Paulo mentioned

fortunately, CMOS is not very fast - lol
at 12 VDC, you're doing well to get a 4040 to count 10 MHz
the width of the spikes is small enough that a gate doesn't decode them   
and - the minimum reset pulse width is probably longer than the spike - lol

this can be a big problem when working with TTL circuits, because they are a bit faster
i really like playing with CMOS   :t
low power consumption - good noise immunity - wide operating range - inexpensive
it's great for things that don't need to haul ass   :P

anyways.....
as you can see, it wouldn't take much to use a synchronous counter
we only need 6 stages
with a little extra circuitry, i could make a near-squarewave output, too
but, for what he wants to do, my original cicuit will work fine

[georg]

An RC circuit could solve the problem, like Dave's schematics.

[georg]

like a high band filter;
                                    C
          And Gate >-------| |---------------------> Reset
                                                |
                                                |
                                               | | R
                                               | |
                                                |
                                               \/
                                             GND

[Paulo]

How about?

[georg]

that's a good one, but you can make Reset the real output, with another AND acting as a follower, and a high-band filter, are two options anyway. EdITED: with the solution you provide.

[Paulo]

One could certainly use the RESET output as the main output.
To buffer one could use another gate or even a BS170 type FET if another gate was not available.
The FET would provide a low impedance output whilst not loading the RC circuit like a BJT would.

Luckily the 4082B has two quad input AND gates so could use the second one to buffer the RESET output.

[georg]

No adding cost with that AND gate, the package for a four input AND come with two gates I believe.

[Paulo]

Very true, I modified my previous post.