UASM 2.36 Update Release

[jj2007]

include \Masm32\MasmBasic\Res\JBasic.inc

myVal qword 0

Init            ; OPT_64 1
  PrintLine Chr$("This code was assembled with ", @AsmUsed$(1), " in ", jbit$, "-bit format")

@inc_s:
   inc myVal
@inc_endp:

@inc_rax_s:
   mov rax, offset myVal
   inc qword ptr [rax]
@inc_rax_endp:

   CodeSize @inc
   CodeSize @inc_rax

   Inkey Str$("myVal=%i", myVal)
EndOfCode

Output:

Code Select Expand

This code was assembled with HJWasm32 in 64-bit format
7       bytes for @inc
13      bytes for @inc_rax
myVal=2

So where is the problem? Why is inc qword ptr [rax] better?

[aw27]

So where is the problem? Why is inc qword ptr [rax] better?

Who told is better in size? IP-Relative addresses are shorter, otherwise will not be chosen as default. If you have an address very far away beyond 32 bit range, you need to reach it by an absolute address. 
My example should have been
   mov rax, myAddress ; address stored in a variable
   inc qword ptr [rax]

[habran]

You should be aware that INC in  IP-Relative addressing can be used only for DW0RD addresses, so:
    inc qword ptr [8C2100Dh]    ; this is OK
    inc qword ptr [80C2100Dh]  ; error A2070: invalid instruction operands
MOV  can be used for 64 bit IP-Relative addresses.

[jj2007]

If you have an address very far away beyond 32 bit range, you need to reach it by an absolute address.

How could this happen? Just curious, really, it's not a provocative question. Can the data and the code sections be more than 32 bits apart?

[habran]

check this:

    inc qword ptr [0C2100Dh]
    inc dword ptr [0C2100Dh]
    inc word ptr [0C2100Dh]
    inc byte ptr [0C2100Dh]
    dec qword ptr [0C2100Dh]
    dec dword ptr [0C2100Dh]
    dec word ptr [0C2100Dh]
    dec byte ptr [0C2100Dh]
    mov [00007FF6601D1010h],rax
    mov [00007FF8807FF660h],eax
    mov [00007FF8807FF660h],ax
    mov [00007FF8807FF660h],al
    mov rax,[00007FF6601D1010h]
    mov eax,[00007FF6601D1010h]
    mov ax,[00007FF6601D1010h]
    mov al,[00007FF6601D1010h]
    mov rax,[0C2100Dh]
    mov eax,[0C2100Dh]
    mov  ax,[0C2100Dh]
    mov  al,[0C2100Dh]
    mov [0C2100Dh],rax
    mov [0C2100Dh],eax
    mov [0C2100Dh],ax
    mov [0C2100Dh],al
    add [0C2100Dh],rax
    add [0C2100Dh],eax
    add [0C2100Dh],ax
    add [0C2100Dh],al
    sub [0C2100Dh],rax
    sub [0C2100Dh],eax
    sub [0C2100Dh],ax
    sub [0C2100Dh],al
    add  rax,[0C2100Dh]
    add  eax,[0C2100Dh]
    add  ax,[0C2100Dh]
    add  al,[0C2100Dh]
    sub  rax,[0C2100Dh]
    sub  eax,[0C2100Dh]
    sub  ax,[0C2100Dh]
    sub  al,[0C2100Dh]

ml64 assembles to:

Code Select Expand


00007FF6A4461010 48 FF 04 25 0D 10 C2 00       inc  qword ptr [0C2100Dh] 
00007FF6A4461018 FF 04 25 0D 10 C2 00          inc  dword ptr [0C2100Dh] 
00007FF6A446101F 66 FF 04 25 0D 10 C2 00       inc  word ptr [0C2100Dh] 
00007FF6A4461027 FE 04 25 0D 10 C2 00          inc  byte ptr [0C2100Dh] 
00007FF6A446102E 48 FF 0C 25 0D 10 C2 00       dec  qword ptr [0C2100Dh] 
00007FF6A4461036 FF 0C 25 0D 10 C2 00          dec  dword ptr [0C2100Dh] 
00007FF6A446103D 66 FF 0C 25 0D 10 C2 00       dec  word ptr [0C2100Dh] 
00007FF6A4461045 FE 0C 25 0D 10 C2 00          dec  byte ptr [0C2100Dh] 
00007FF6A446104C 48 A3 10 10 1D 60 F6 7F 00 00 mov  qword ptr [00007FF6601D1010h],rax 
00007FF6A4461056 A3 60 F6 7F 80 F8 7F 00 00    mov  dword ptr [00007FF8807FF660h],eax 
00007FF6A446105F 66 A3 60 F6 7F 80 F8 7F 00 00 mov  word ptr [00007FF8807FF660h],ax 
00007FF6A4461069 A2 60 F6 7F 80 F8 7F 00 00    mov  byte ptr [00007FF8807FF660h],al 
00007FF6A4461072 48 A1 10 10 1D 60 F6 7F 00 00 mov  rax,qword ptr [00007FF6601D1010h] 
00007FF6A446107C A1 10 10 1D 60 F6 7F 00 00    mov  eax,dword ptr [00007FF6601D1010h] 
00007FF6A4461085 66 A1 10 10 1D 60 F6 7F 00 00 mov  ax,word ptr [00007FF6601D1010h] 
00007FF6A446108F A0 10 10 1D 60 F6 7F 00 00    mov  al,byte ptr [00007FF6601D1010h] 
00007FF6A4461098 48 8B 04 25 0D 10 C2 00       mov  rax,qword ptr [0C2100Dh] 
00007FF6A44610A0 8B 04 25 0D 10 C2 00          mov  eax,dword ptr [0C2100Dh] 
00007FF6A44610A7 66 8B 04 25 0D 10 C2 00       mov  ax,word ptr [0C2100Dh] 
00007FF6A44610AF 8A 04 25 0D 10 C2 00          mov  al,byte ptr [0C2100Dh] 
00007FF6A44610B6 48 89 04 25 0D 10 C2 00       mov  qword ptr [0C2100Dh],rax 
00007FF6A44610BE 89 04 25 0D 10 C2 00          mov  dword ptr [0C2100Dh],eax 
00007FF6A44610C5 66 89 04 25 0D 10 C2 00       mov  word ptr [0C2100Dh],ax 
00007FF6A44610CD 88 04 25 0D 10 C2 00          mov  byte ptr [0C2100Dh],al 
00007FF6A44610D4 48 01 04 25 0D 10 C2 00       add  qword ptr [0C2100Dh],rax 
00007FF6A44610DC 01 04 25 0D 10 C2 00          add  dword ptr [0C2100Dh],eax 
00007FF6A44610E3 66 01 04 25 0D 10 C2 00       add  word ptr [0C2100Dh],ax 
00007FF6A44610EB 00 04 25 0D 10 C2 00          add  byte ptr [0C2100Dh],al 
00007FF6A44610F2 48 29 04 25 0D 10 C2 00       sub  qword ptr [0C2100Dh],rax 
00007FF6A44610FA 29 04 25 0D 10 C2 00          sub  dword ptr [0C2100Dh],eax 
00007FF6A4461101 66 29 04 25 0D 10 C2 00       sub  word ptr [0C2100Dh],ax 
00007FF6A4461109 28 04 25 0D 10 C2 00          sub  byte ptr [0C2100Dh],al 
00007FF6A4461110 48 03 04 25 0D 10 C2 00       add  rax,qword ptr [0C2100Dh] 
00007FF6A4461118 03 04 25 0D 10 C2 00          add  eax,dword ptr [0C2100Dh] 
00007FF6A446111F 66 03 04 25 0D 10 C2 00       add  ax,word ptr [0C2100Dh] 
00007FF6A4461127 02 04 25 0D 10 C2 00          add  al,byte ptr [0C2100Dh] 
00007FF6A446112E 48 2B 04 25 0D 10 C2 00       sub  rax,qword ptr [0C2100Dh] 
00007FF6A4461136 2B 04 25 0D 10 C2 00          sub  eax,dword ptr [0C2100Dh] 
00007FF6A446113D 66 2B 04 25 0D 10 C2 00       sub  ax,word ptr [0C2100Dh] 



[aw27]

You should be aware that INC in  IP-Relative addressing can be used only for DW0RD addresses, so:
    inc qword ptr [8C2100Dh]    ; this is OK
    inc qword ptr [80C2100Dh]  ; error A2070: invalid instruction operands
MOV  can be used for 64 bit IP-Relative addresses.

In RIP-relative addressing the offset, or displacement, is limited to 32-bit. That's why we need absolute addressing in some cases.

[aw27]

If you have an address very far away beyond 32 bit range, you need to reach it by an absolute address.

How could this happen? Just curious, really, it's not a provocative question. Can the data and the code sections be more than 32 bits apart?

Not provocative at all, you are just curious.  :lol:
64-bit Windows applications have 8 terabytes of virtual memory address space, from 0x00000000000 through 0x7FFFFFFFFFF
Try to use a memory mapped files or VirtualAlloc to have pointers to far away memory.

[jj2007]

64-bit Windows applications have 8 terabytes of virtual memory address space, from 0x00000000000 through 0x7FFFFFFFFFF
Try to use a memory mapped files or VirtualAlloc to have pointers to far away memory.

Yes, that is known. But we are talking about RIP-relative addressing, i.e. current value of CODE as in RIP vs position in DATA section. Both memory mapped files and VirtualAlloc return pointers that you will store in a register. If I am wrong, please explain, I want to understand this properly.

[aw27]

Yes, that is known. But we are talking about RIP-relative addressing, i.e. current value of CODE as in RIP vs position in DATA section. Both memory mapped files and VirtualAlloc return pointers that you will store in a register. If I am wrong, please explain, I want to understand this properly.

OK then  :t

Something that is wrong and I think that it is what habran is working on is this:
myfunc proc
   mov rax, 07FFFFh
   mov rdx, [07FFFFh]
   ret
myfunc endp

Assembles in UASM to:
00000001`3fac1025 48c7c0ffff0700  mov     rax,7FFFFh
00000001`3fac102c 48c7c2ffff0700  mov     rdx,7FFFFh
00000001`3fac1037 c3              ret

and in MASM to:

00000001`3f9d1021 48c7c0ffff0700  mov     rax,7FFFFh
00000001`3f9d1028 488b1425ffff0700 mov     rdx,qword ptr [7FFFFh]
00000001`3f9d1030 c3              ret

[habran]

That is correct, but not only 32 bit addresses,  64 bit as well, as you can see here:

Code Select Expand


00007FF6A446104C 48 A3 10 10 1D 60 F6 7F 00 00 mov  qword ptr [00007FF6601D1010h],rax 
00007FF6A4461056 A3 60 F6 7F 80 F8 7F 00 00    mov  dword ptr [00007FF8807FF660h],eax 
00007FF6A446105F 66 A3 60 F6 7F 80 F8 7F 00 00 mov  word ptr [00007FF8807FF660h],ax 
00007FF6A4461069 A2 60 F6 7F 80 F8 7F 00 00    mov  byte ptr [00007FF8807FF660h],al 
00007FF6A4461072 48 A1 10 10 1D 60 F6 7F 00 00 mov  rax,qword ptr [00007FF6601D1010h] 
00007FF6A446107C A1 10 10 1D 60 F6 7F 00 00    mov  eax,dword ptr [00007FF6601D1010h] 
00007FF6A4461085 66 A1 10 10 1D 60 F6 7F 00 00 mov  ax,word ptr [00007FF6601D1010h] 
00007FF6A446108F A0 10 10 1D 60 F6 7F 00 00    mov  al,byte ptr [00007FF6601D1010h] 

RIP relative addressing accepts only DWORD displacement

IP addressing is giving you access to 64 bit addresses without additional index or base register, so if you know what are you doing it could be useful, especially for writing debugger 8)
However, only MOV is able to access 64 bit addresses, anyway, don't look a gift horse in the mouth :P

[aw27]

That is correct, but not only 32 bit addresses,  64 bit as well, as you can see here:

Code Select Expand


00007FF6A446104C 48 A3 10 10 1D 60 F6 7F 00 00 mov  qword ptr [00007FF6601D1010h],rax 
00007FF6A4461056 A3 60 F6 7F 80 F8 7F 00 00    mov  dword ptr [00007FF8807FF660h],eax 
00007FF6A446105F 66 A3 60 F6 7F 80 F8 7F 00 00 mov  word ptr [00007FF8807FF660h],ax 
00007FF6A4461069 A2 60 F6 7F 80 F8 7F 00 00    mov  byte ptr [00007FF8807FF660h],al 
00007FF6A4461072 48 A1 10 10 1D 60 F6 7F 00 00 mov  rax,qword ptr [00007FF6601D1010h] 
00007FF6A446107C A1 10 10 1D 60 F6 7F 00 00    mov  eax,dword ptr [00007FF6601D1010h] 
00007FF6A4461085 66 A1 10 10 1D 60 F6 7F 00 00 mov  ax,word ptr [00007FF6601D1010h] 
00007FF6A446108F A0 10 10 1D 60 F6 7F 00 00    mov  al,byte ptr [00007FF6601D1010h] 

RIP relative addressing accepts only DWORD displacement

IP addressing is giving you access to 64 bit addresses without additional index or base register, so if you know what are you doing it could be useful, especially for writing debugger 8)
However, only MOV is able to access 64 bit addresses, anyway, don't look a gift horse in the mouth :P

x64 Architecture - Addressing Modes, as explained by Microsoft:
A special form of the mov instruction has been added for 64-bit immediate constants or constant addresses. For all other instructions, immediate constants or constant addresses are still 32 bits.

So, there is no room for anything else.